Multilayer ceramic capacitor
US-2015340155-A1 · Nov 26, 2015 · US
Multilayer ceramic capacitor and board having the same
US10770233B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10770233-B2 |
| Application number | US-201916444350-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 18, 2019 |
| Priority date | Jan 6, 2015 |
| Publication date | Sep 8, 2020 |
| Grant date | Sep 8, 2020 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A multilayer ceramic capacitor includes a ceramic body including an active portion including dielectric layers and internal electrodes that are alternately stacked and a margin portion disposed on outer surfaces of the active portion; and external electrodes disposed on outer surfaces of the ceramic body. The margin portion includes an inner half adjacent to the active portion and an outer half adjacent to the edge of the ceramic body, and a porosity of the inner half is greater than a porosity of the outer half.
First claim
Opening claim text (preview).
What is claimed is: 1. A multilayer ceramic capacitor comprising: a ceramic body including an active portion including dielectric layers and internal electrodes that are alternately stacked in a thickness direction and a margin portion disposed on outer surfaces of the active portion; and external electrodes disposed on outer surfaces of the ceramic body, wherein the margin portion includes an inner half adjacent to the active portion and an outer half adjacent to an edge of the ceramic body, and a porosity of the inner half is greater than a porosity of the outer half, and the porosity of the inner half is 0.06% to 2.0%, and the porosity of the outer half is 0.05% or less, in margin portions disposed on upper and lower surfaces of the active portion in the thickness direction, average sizes of dielectric grains of the inner half and the outer half are different from each other, and the inner half of the margin portion covering upper, lower and side surfaces of the active portion is made of a same composition. 2. The multilayer ceramic capacitor of claim 1 , wherein an average size of each pore in the inner half is 0.05 μm to 0.1 μm. 3. The multilayer ceramic capacitor of claim 1 , wherein an average size of each pore in the outer half is 0.015 μm to 0.03 μm. 4. A board having a multilayer ceramic capacitor, comprising: a printed circuit board on which a plurality of electrode pads are disposed; and the multilayer ceramic capacitor installed on the printed circuit board, wherein the multilayer ceramic capacitor includes a ceramic body including an active portion including dielectric layers and internal electrodes that are alternately stacked in a thickness direction and a margin portion disposed on outer surfaces of the active portion, and external electrodes disposed on outer surfaces of the ceramic body, the margin portion includes an inner half adjacent to the active portion and an outer half adjacent to an edge of the ceramic body, and a porosity of the inner half is greater than a porosity of the outer half, and the porosity of the inner half is 0.06% to 2.0%, and the porosity of the outer half is 0.05% or less, in margin portions disposed on upper and lower surfaces of the active portion in the thickness direction, average sizes of dielectric grains of the inner half and the outer half are different from each other, and the inner half of the margin portion covering upper, lower and side surfaces of the active portion is made of a same composition. 5. The board having a multilayer ceramic capacitor of claim 4 , wherein an average size of each pore in the inner half is 0.05 μm to 0.1 μm. 6. The board having a multilayer ceramic capacitor of claim 4 , wherein an average size of each pore in the outer half is 0.015 μm to 0.03 μm.
Assignees
Inventors
Classifications
- H01G4/30Primary
Stacked capacitors (H01G4/33 takes precedence) · CPC title
having edge contacts, e.g. leadless chip capacitors, chip carriers · CPC title
electrically connecting two or more layers of a stacked or rolled capacitor · CPC title
- H01G4/1209Primary
characterised by the ceramic dielectric material (H01G4/1272, H01G4/1281 take precedence) · CPC title
related technologies for production or treatment of textile or flexible materials or products thereof, including footwear · CPC title
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- What does patent US10770233B2 cover?
- A multilayer ceramic capacitor includes a ceramic body including an active portion including dielectric layers and internal electrodes that are alternately stacked and a margin portion disposed on outer surfaces of the active portion; and external electrodes disposed on outer surfaces of the ceramic body. The margin portion includes an inner half adjacent to the active portion and an outer half…
- Who is the assignee on this patent?
- Samsung Electro Mech
- What technology area does this patent fall under?
- Primary CPC classification H01G4/30. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 08 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).