SRAM based authentication circuit

Patent metadata

Field	Value
Publication number	US-10770134-B2
Application number	US-201816202584-A
Country	US
Kind code	B2
Filing date	Nov 28, 2018
Priority date	Oct 7, 2016
Publication date	Sep 8, 2020
Grant date	Sep 8, 2020

Abstract

A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.

First claim

What is claimed is:

1. A memory device, comprising:
a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state;
a physically unclonable function (PUF) generator, comprising:
a first sense amplifier, coupled to the plurality of memory cells, wherein while at least some of the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, located in first and second columns of the memory cell array, respectively, and based on the comparison, provide a first output signal for generating a first PUF signature; and

a pre-charge/pre-discharge (PC/PD) circuit that is coupled to the plurality of memory cells, wherein the PC/PD circuit is configured to pre-charge bit lines of the first and second columns to either a positive supply voltage or to ground based on a data state of the plurality of memory cells before the first and second memory cells are accessed.

2. The memory device of claim 1 , wherein the first and second memory cells are arranged in a same row of the memory cell array and arranged in a first column and a second column of the memory cell array, respectively, and wherein the first and second columns are next to each other without additional column therebetween.

3. The memory device of claim 2 , wherein the first sense amplifier is coupled to a bit line of the first column and a bit line of the second column, and wherein the bit line of the first column is coupled to the first memory cell and the bit line of the second column is coupled to the second memory cell.

4. The memory device of claim 3 , further comprising a pre-charge/pre-discharge (PC/PD) circuit that is coupled to the plurality of memory cells.

5. The memory device of claim 4 , wherein when the data state is a logical 0, the PC/PD circuit is configured to pre-charge the bit lines of the first and second columns to a positive supply voltage before the data states of the first and second memory cells are read.

6. The memory device of claim 5 , wherein when the data state is a logical 1, the PC/PD circuit is configured to pre-discharge the bit lines of the first and second columns to ground before the data states of the first and second memory cells are read.

7. The memory device of claim 5 , wherein during the data states of the first and second memory cells are being read, the first and second cells are supplied with a voltage level that is lower than the positive supply voltage.

8. The memory device of claim 1 , wherein the PUF generator further comprises:
a second sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being read by respective sense amplifiers different from the second sense amplifier, the second sense amplifier is configured to compare either respective discharging rates or respective charging rates of third and fourth memory cells of the plurality of memory cells that are adjacent to each other, and based on the comparison, provide a second output signal for generating the first PUF signature.

9. A memory device, comprising:
a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state;
a physically unclonable function (PUF) generator, comprising:
a first sense amplifier, coupled to first and second memory cells of the plurality of memory cells, and
a second sense amplifier, also coupled to the first and second memory cells of the plurality of memory cells, wherein the first and second memory cells are located in first and second columns of the memory cell array, respectively; and

a pre-charge/pre-discharge (PC/PD) circuit that is coupled to the plurality of memory cells, wherein the PC/PD circuit is configured to pre-charge bit lines of the first and second columns to either a positive supply voltage or to ground based on a data state of the plurality of memory cells before the first and second memory cells are accessed.

10. The memory device of claim 9 , wherein
while the data states of the plurality of memory cells are being read by respective sense amplifiers different from the first and second sense amplifiers, the first sense amplifier is configured to compare respective discharging rates of the first and second memory cells, the second sense amplifier is configured to compare respective charging rates of the first and second memory cells, and based on a first voltage difference according to the comparison on the discharging rates, the first amplifier is configured to provide a first output signal and based on a second voltage difference according to the comparison on the charging rates, the second sense amplifier is configured to provide a second output signal, and
wherein the first and second output signals are used for generating a PUF signature, and wherein the first sense amplifier is coupled to a bit line of a first column and a bit line of a second column, wherein the second sense amplifier is coupled to a bit bar line of the first column and a bit bar line of the second column, and wherein the bit line and the bit bar line of the first column is coupled to the first memory cell and the bit line and the bit bar line of the second column is coupled to the second memory cell.

11. The memory device of claim 10 , wherein the first and second memory cells are arranged in a same row of the memory cell array and arranged in the first column and the second column of the memory cell array, respectively, and wherein the first and second columns are next to each other without an additional column therebetween.

12. The memory device of claim 10 , wherein when the data state is a logical 0, the PC/PD circuit is configured to pre-charge the bit lines of the first and second columns to a positive supply voltage before the data states of the first and second memory cells are read, and pre-discharge the bit bar lines of the first and second columns to ground before the data states of the first and second memory cells are read.

13. The memory device of claim 10 , wherein when the data state is a logical 1, the PC/PD circuit is configured to pre-discharge the bit lines of the first and second columns to ground before the data states of the first and second memory cells are read, and pre-charge the bit bar lines of the first and second columns to the positive supply voltage before the data states of the first and second memory cells are read.

14. The memory device of claim 10 , wherein during the data states of the first and second memory cells are being read, the first and second cells are supplied with a voltage level that is lower than positive supply voltage.

15. A memory device, comprising:
a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state;
a physically unclonable function (PUF) generator, coupled to the plurality of memory cells, that comprises:
a first sense amplifier, and
a column decoder, coupled between the plurality of memory cells and the first sense amplifier, that comprises at least four switches wherein each of the switches is coupled to one of four columns of the memory cell array, wherein while the data states of the plurality of memory cells are being read, the column decoder is configured to assert two of the four switches so as to allow the first sense amplifier to compare either respective discharging rates or respective charging rates of first and second memory cells of the plurality of memory cell

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Chien-Chen
• Chan Wei-Min
• Lin Chih-Yu
• Lu Shih-Lien Linus
• Chen Yen-Huei

Classifications

• G11C11/418

  Address circuits · CPC title

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C7/24

  Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells · CPC title

• G06F21/73 Primary

  by creating or determining hardware identification, e.g. serial numbers · CPC title

• G11C11/413

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title