Input termination circuits for high speed receivers

Patent metadata

Field	Value
Publication number	US-10764092-B2
Application number	US-201916681525-A
Country	US
Kind code	B2
Filing date	Nov 12, 2019
Priority date	Aug 10, 2018
Publication date	Sep 1, 2020
Grant date	Sep 1, 2020

Abstract

The present invention is directed to communication systems and electrical circuits. According to an embodiment, an input termination circuit includes a first attenuation resistor and a second attenuation resistor. The resistance values of these two resistors are adjusted in opposite directions to maintain a stable output impedance. There are other embodiments as well.

First claim

What is claimed is:

1. A receiver apparatus comprising:
an input termination circuit comprising:
a first inductor connected to an input terminal;
a first input resistor connected to the first inductor;
a second inductor connected to the first input resistor;
a first attenuation resistor connected to the first input resistor and the second inductor, the first attenuation resistor being adjustable by a first control signal;
an output inductor connected to the second inductor;
a second attenuation resistor connected to the second inductor and the output inductor, the second attenuation resistor being adjustable by a second control signal;
an equalizer coupled to the output inductor; and
an amplifier coupled to the equalizer.

2. The apparatus of claim 1 further comprising a loss-of-signal detection (LOSD) module coupled to the input terminal.

3. The apparatus of claim 1 further a second input resistor connected to the first inductor and the first input resistor.

4. The apparatus of claim 1 further comprising a clock-and-data recovery (CDR) module.

5. The apparatus of claim 1 wherein the receiver is a SerDes receiver, the SerDes receiver comprising an analog front end.

6. The apparatus of claim 1 wherein the input terminal circuit is characterized by an output impedance matching an input impedance of the equalizer.

7. A method of adjusting an input termination circuit, wherein the input termination circuit comprising a first attenuation resistor and a second attenuation resistor, the method comprising:
initiating attenuation parameters associated with the input termination circuit, the attenuation parameters including a first resistance value associated with the first attenuation resistor and a second resistance value associated with the second attenuation resistor;
adjusting the first resistance value based at least on a strength of data signals;
adjusting the second resistance value based at least on the first resistance value;
determining a bandwidth associated with the input termination circuit;
adjusting the second resistance value based on the bandwidth and the strength of the data signals; and
receiving the data signals using the input termination circuit.

8. The method of claim 7 further comprising generating control signals for adjusting the first resistance value and the second resistance value.

9. The method of claim 7 further comprising adjusting a resistance value of an input resistor.

10. A receiver apparatus comprising:
an input termination circuit comprising:
a first inductor connected to an input terminal;
a first input resistor connected to the first inductor;
a second inductor connected to the first input resistor;
a first attenuation resistor connected to the first input resistor and the second inductor, the first attenuation resistor being adjustable by a first control signal;
a first output inductor connected to the second inductor, the output inductor being adjustable to match input capacitance;
a second attenuation resistor connected to the second inductor and the output inductor, the second attenuation resistor being adjustable by a second control signal; and
an equalizer coupled to the output inductor, the equalizer being associated with an input capacitance.

11. The apparatus of claim 10 further comprising an input terminal configured to receive analog signal, the input terminal being coupled to the input termination circuit.

12. The apparatus of claim 10 further comprising a control module for generating the first control signal and the second control signal.

13. The apparatus of claim 10 wherein first attenuation resistor and the second attenuation resistor are associated with an output impedance.

14. The apparatus of claim 10 wherein a ratio between the first attenuation resistor and the second attenuation resistor is associated with a peaking frequency.

15. The apparatus of claim 10 wherein the equalizer comprises an continuous time linear equalizer.

16. The apparatus of claim 10 further comprising a comprising a loss-of-signal detection (LOSD) module coupled to the input terminal.

17. The apparatus of claim 10 wherein the input terminal circuit is characterized by an output impedance matching an input impedance of the CTLE.

18. The apparatus of claim 10 further comprising a clock-and-data recovery (CDR) module.

19. The apparatus of claim 10 further comprising a second output inductor coupled to the second attenuation resistor.

20. The apparatus of claim 10 further comprising a second input resistor coupled to the first input inductor and the first input resistor.

Assignees

• Inphi Corp

Inventors

• Forey Simon
• Nagulapalli Rajasekhar
• Mishra Parmanand

Classifications

• H04L25/0278 Primary

  Arrangements for impedance matching · CPC title

• H04L25/03878

  Line equalisers; line build-out devices · CPC title

• H04L25/0292

  Arrangements specific to the receiver end · CPC title

• H04B1/18

  Input circuits, e.g. for coupling to an antenna or a transmission line (coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H) · CPC title

• H04L1/20

  using signal quality detector · CPC title