Loss of signal detection circuit

Patent metadata

Field	Value
Publication number	US-10763841-B2
Application number	US-201916535557-A
Country	US
Kind code	B2
Filing date	Aug 8, 2019
Priority date	Aug 9, 2018
Publication date	Sep 1, 2020
Grant date	Sep 1, 2020

Abstract

Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.

First claim

What is claimed is:

1. A system, comprising:
an embedded Universal Serial Bus 2 (eUSB2) device having a loss of signal detector comprising:
a first differential comparator having a first input coupled to a first node, a second input coupled to a second node, and an output coupled to a third node;
a second differential comparator having a first input coupled to the second node, a second input coupled to the first node, and an output coupled to a fourth node;
a first feedback circuit coupled between the third node and the fourth node;
a first inverter coupled between the third node and a fifth node;
a second inverter coupled between the fourth node and a sixth node; and
a first logic circuit having a first input coupled to the fifth node, a second input coupled to the sixth node, and an output.

2. The system of claim 1 , further comprising a second positive feedback circuit coupled between the fifth node and the sixth node.

3. The system of claim 1 , wherein the first logic circuit comprises an inverting AND (NAND) logic circuit.

4. The system of claim 3 , further comprising a third inverter coupled between the output of the first logic circuit and a seventh node.

5. The system of claim 1 , further comprising:
a second logic circuit having a first input coupled to the third node, a second input coupled to the fourth node, and an output;
a resistor coupled between the output of the second logic circuit and an eighth node; and
a capacitor coupled between the eighth node and a ground node.

6. The system of claim 5 , wherein a switch control signal is present at the eighth node, and wherein the switch control signal controls enablement and disablement of the first feedback circuit.

7. The system of claim 1 , wherein the feedback circuit comprises:
a first switch coupled between the third node and a ninth node, the first switch controlled by a switch control signal;
a second switch coupled between the fourth node and a tenth node, the second switch controlled by the switch control signal;
a fourth inverter having an input coupled to the tenth node and an output coupled to the ninth node; and
a fifth inverter having an input coupled to the ninth node and an output coupled to the tenth node.

8. A circuit, comprising:
a first differential comparator having a first input coupled to a first node, a second input coupled to a second node, and an output coupled to a third node;
a second differential comparator having a first input coupled to the second node, a second input coupled to the first node, and an output coupled to a fourth node;
a first inverter coupled between the third node and a fifth node;
a second inverter coupled between the fourth node and a sixth node;
a first logic circuit having a first input coupled to the fifth node, a second input coupled to the sixth node, and an output;
a second logic circuit having a first input coupled to the third node, a second input coupled to the fourth node, and an output;
a resistor coupled between the output of the second logic circuit and a seventh node;
a capacitor coupled between the seventh node and a ground node; and
a first feedback circuit coupled between the third node and the fourth node and having a control input coupled to the seventh node.

9. The circuit of claim 8 , wherein the first feedback circuit comprises:
a first switch coupled between the third node and an eighth node, the first switch having a control input coupled to the seventh node;
a second switch coupled between the fourth node and a ninth node, the second switch having a control input coupled to the seventh node;
a third inverter having an input coupled to the ninth node and an output coupled to the eighth node; and
a fourth inverter having an input coupled to the eighth node and an output coupled to the ninth node.

10. The circuit of claim 8 , further comprising a second feedback circuit coupled between the fifth node and the sixth node, the second feedback circuit comprising:
a third switch coupled between the fifth node and an eleventh node, the third switch having a control input coupled to the seventh node;
a fourth switch coupled between the sixth node and a twelfth node, the fourth switch having a control input coupled to the seventh node;
a fifth inverter having an input coupled to the eleventh node and an output coupled to the twelfth node; and
a sixth inverter having an input coupled to the twelfth node and an output coupled to the eleventh node.

11. The circuit of claim 8 , wherein the first logic circuit comprises an inverting AND (NAND) logic circuit.

12. The circuit of claim 11 , further comprising a seventh inverter coupled between the output of the first logic circuit and a thirteenth node.

13. The circuit of claim 8 , wherein the second logic circuit comprises an OR logic circuit.

14. The circuit of claim 8 , further comprising:
a second feedback circuit coupled between the third node and the fourth node; and
a third feedback circuit coupled between the fifth node and the sixth node.

15. A circuit, comprising:
a first inverter coupled between a first node and a second node;
a second inverter coupled between a third node and a fourth node;
a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output; and
a first feedback circuit coupled between the first node and the third node and having a control input, the first feedback circuit comprising:
a first switch coupled between the first node and a fifth node, the first switch having a control input;
a second switch coupled between the third node and a sixth node, the second switch having a control input;
a third inverter having an input coupled to the sixth node and an output coupled to the fifth node; and
a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.

16. The circuit of claim 15 , further comprising:
a second logic circuit having a first input coupled to the first node, a second input coupled to the second node, and an output;
a resistor coupled between the output of the second logic circuit and a seventh node;
a capacitor coupled between the seventh node and a ground node,
wherein the control input of the first switch is coupled to the seventh node and the control input of the second switch is coupled to the seventh node.

17. The circuit of claim 16 , further comprising:
a first differential comparator having a positive input configured to couple to a positive polarity of a differential input signal, a negative input configured to couple to a negative polarity of the differential input signal, and an output coupled to the first node; and
a second differential comparator having a positive input configured to couple to the negative polarity of the differential input signal, a positive input configured to couple to the positive polarity of the differential input signal, and an output coupled to the third node.

18. The circuit of claim 17 , further comprising:
a second feedback circuit coupled between the second node and the fourth node and having a control input, the second feedback circuit comprising:
a third switch coupled between the second node and an eighth node, the first switch having a control input coupled to the seventh node;
a fourth switch coupled between the fourth node and a ninth node, the second switch having a control input coupled to the seventh node;
a fifth inverter having an input coupled to the ninth node and an output coupled to the eighth node; and
a sixth inv

Assignees

• Texas Instruments Inc

Inventors

• Huang Huanzhang
• Rane Amit

Classifications

• G06F2213/0042

  Universal serial bus [USB] · CPC title

• H03K17/56

  by the use, as active elements, of semiconductor devices (using diodes H03K17/74) · CPC title

• H03K19/003

  Modifications for increasing the reliability {for protection} · CPC title

• G06F13/382 Primary

  using universal interface adapter · CPC title

• H03K17/005 Primary

  with several inputs only · CPC title