Fast startup time for crystal oscillator

Patent metadata

Field	Value
Publication number	US-10763785-B2
Application number	US-201916556249-A
Country	US
Kind code	B2
Filing date	Aug 30, 2019
Priority date	Dec 25, 2017
Publication date	Sep 1, 2020
Grant date	Sep 1, 2020

Abstract

Embodiments can provide individualized controlling of noise injection during startup of a crystal oscillator. In some embodiments, a simple learning block can be placed in parallel to a crystal oscillator circuit to control noise injection during the startup of the crystal oscillator. The learning block can be configured to control the noise injection during the startup of the crystal oscillator by determining whether the crystal oscillator has been stabilized. In some implementations, an adjustment block may be employed to adjust the count determined by the learning block based on one or more characteristics of the crystal oscillator during a startup of the crystal oscillator. In some embodiments, a simple block that creates a negative capacitance can be configured in parallel to the crystal oscillator.

First claim

What is claimed is:

1. A circuit configured for controlling a startup for an oscillator circuit, the circuit comprising:
a learning block configured to:
obtain an oscillation level of a crystal element in the oscillator circuit during a startup of the crystal element;
when the oscillation level is at a predetermined threshold or slightly above the predetermined threshold:
reset a count of the learning block to the predetermined threshold; and
start incrementing the count by clock cycles; and

when the oscillation level the crystal element has reached a predetermined target oscillation level, stop the count; and, wherein

the learning block is configured for deactivating negative capacitance generation for the oscillator circuit, wherein the count is accessible for controlling the deactivation of the negative capacitance generation.

2. The circuit of claim 1 , wherein the learning block is further configured to adjust the count to account for a lead time for deactivate noise injection by a disable mechanism.

3. The circuit of claim 2 , wherein the disable mechanism comprises a tristate buffer.

4. The circuit of claim 1 , wherein the count indicates a time duration in a first startup for the crystal element to stabilize and the count is used to control the deactivation of negative capacitance generation during a second startup for the crystal element, the second startup being after the first startup.

5. The circuit of claim 1 , wherein the learning block comprises:
a determinator configured to determine whether the oscillation level of the crystal element has reached the predetermined target oscillation level; and
a counter configured to increment the count when the oscillation level of the crystal element has not reached the predetermined target oscillation level, and to stop the count when the oscillation level of a crystal element has reached the predetermined target oscillation level.

6. The circuit of claim 1 , further comprising an adjustment block operatively connected to the learning block, the adjustment block being configured to:
receive one or more values indicating one or more measured characteristics of the oscillator circuit during a current startup of the oscillator circuit;
obtain the count from the learning block;
adjust the count based on the one or more values indicating the one or more measured characteristics of the oscillator circuit; and
store the adjusted count in a buffer.

7. The circuit of claim 6 , wherein the one or more characteristics of the oscillator circuit includes a temperature of the crystal element.

8. The circuit of claim 6 , wherein the adjustment block is further configured to fetch the adjusted count in the buffer to the disable mechanism in the current startup for the crystal element.

9. The circuit of claim 1 , further comprising a negative impedance block operatively connected to the oscillation circuit, and configured to generate the negative capacitance to cancel impedance of the crystal element.

10. The circuit of claim 9 , wherein the negative capacitance generated by the impedance block includes a combination of negative resistance and capacitance.

11. The circuit of claim 9 , wherein the negative capacitance generated by the impedance block includes a float negative resistance around 4 pF.

12. A method for controlling deactivation of noise injection during a startup for an oscillator circuit, the method being implemented by a circuit comprising a learning block, the circuit being operatively connected to the oscillator circuit, the method comprising:
obtaining an oscillation level of a crystal element in the oscillator circuit during a startup of the crystal element;
when the oscillation level is at a predetermined threshold or slightly above the predetermined threshold:
resetting a count of the learning block to the predetermined threshold; and
starting incrementing the count by clock cycles; and

when the oscillation level the crystal element has reached the predetermined target oscillation level, stopping the count; and, wherein
the learning block is configured for deactivating negative capacitance generation for the oscillator circuit, wherein the count is accessible for controlling the deactivation of the negative capacitance generation.

13. The method of claim 12 , wherein the method further comprises adjusting the count to account for a lead time for deactivate noise injection by a disable mechanism.

14. The method of claim 13 , wherein the count indicates a time duration in a first startup for the crystal element to stabilize and the count is used by the disable mechanism to control the deactivation of the noise injection during a second startup for the crystal element, the second startup being after the first startup.

15. The method of claim 12 , wherein the circuit further comprises an adjustment block operatively connected to the learning block, the method being further implemented by the adjustment block, the method further comprising:
receiving one or more values indicating one or more measured characteristics of the oscillator circuit during a current startup of the oscillator circuit;
obtaining the count from the learning block;
adjusting the count based on the one or more values indicating the one or more measured characteristics of the oscillator circuit; and
storing the adjusted count in a buffer.

16. The method of claim 15 , wherein the one or more characteristics of the oscillator circuit includes a temperature of the crystal element.

17. The method of claim 16 , wherein the method further comprises fetching the adjusted count in the buffer to the disable mechanism in the current startup for the crystal element.

18. The method of claim 12 , wherein the method further comprises a negative impedance block operatively connected to the oscillation circuit, and the method further being further implemented by the negative impedance block, the method further comprising generating the negative capacitance to cancel impedance of the crystal element.

19. The method of claim 18 , wherein the negative impedance generated by the impedance block includes a combination of negative resistance and capacitance.

20. The method of claim 19 , wherein the negative capacitance generated by the impedance block includes a float negative resistance around 4 pF.

Assignees

• Shenzhen Goodix Tech Co Ltd

Inventors

• Abuellil Amr
• Sivasubramaniam Janakan

Classifications

• H03B29/00 Primary

  Generation of noise currents and voltages {(gasfilled discharge tubes with solid cathode specially adapted as noise generators H01J17/005)} · CPC title

• H03B7/00 Primary

  Generation of oscillations using active element having a negative resistance between two of its electrodes (H03B9/00 takes precedence) · CPC title

• H03B1/02

  Structural details of power oscillators, e.g. for heating {(construction of transmitters H04B; features of generators for heating by electromagnetic fields H05B6/00)} · CPC title

• H03B5/36 Primary

  active element in amplifier being semiconductor device ({H03B5/323, H03B5/326} , H03B5/38 take precedence) · CPC title

• H03B5/364

  the amplifier comprising field effect transistors (H03B5/366 takes precedence) · CPC title