Display substrate, method for manufacturing display substrate, display panel, and display device

Patent metadata

Field	Value
Publication number	US-10763450-B2
Application number	US-201816465311-A
Country	US
Kind code	B2
Filing date	Aug 31, 2018
Priority date	Nov 30, 2017
Publication date	Sep 1, 2020
Grant date	Sep 1, 2020

Abstract

The present disclosure provides a display substrate, a method for manufacturing the display substrate, a display panel, and a display device. The display substrate includes: a bonding region, and a plurality of pads disposed at intervals in the bonding region. The pads are spaced apart by an insulating layer, and a groove is set in the insulating layer between at least two adjacent pads. The groove is set in the insulating layer between at least two adjacent pads in the bonding region to enable the ACF to flow to the groove as pressed.

First claim

The invention claimed is:

1. A display substrate, comprising a bonding region; a plurality of pads at intervals in the bonding region; and an insulating layer for spacing apart the pads;
wherein,
a groove is in the insulating layer between at least two adjacent pads, the groove is configured to accommodate an overflow anisotropic conductive film during a bonding process; and
wherein,
the display substrate further comprising: a base substrate, an active layer, a first metal layer, a second metal layer, a drain/source metal layer, a flat layer, an anode, a pixel defining layer, a light-emitting layer and a cathode;
the insulating layer comprises a buffer layer, a first insulating layer, a second insulating layer, and an interlayer insulating layer;
the buffer layer, the active layer, the first insulating layer, the first metal layer, the second insulating layer, the second metal layer, the interlayer insulating layer, the source/drain metal layer, the flat layer, the anode, the pixel defining layer, the light-emitting layer, and the cathode are sequentially on the base substrate; and
a depth of the groove is no less than a sum of thicknesses of the second insulating layer and the interlayer insulating layer.

2. The display substrate according to claim 1 , wherein the groove is between any two adjacent pads.

3. The display substrate according to claim 1 , wherein the pads comprise input pads and output pads, and the bonding region comprises a first region and a second region at intervals, wherein the input pads are in the first region, the output pads are in the second region, and the groove is between the first region and the second region.

4. The display substrate according to claim 1 , wherein a depth of the groove is no less than a thickness of an uppermost sub-insulating layer among the plurality of sub-insulating layers, and the uppermost sub-insulating layer is a sub-insulating layer farthest from the base substrate.

5. The display substrate according to claim 1 , wherein a depth of the groove is equal to a thickness of the insulating layer.

6. A method for manufacturing a display substrate, comprising:
providing a base substrate; and
forming film layers on the base substrate and setting a groove in a bonding region of the display substrate;
wherein the display substrate is the display substrate according to claim 1 , and
the film layers comprise an active layer, a first metal layer, a second metal layer, a drain/source metal layer, a flat layer, an anode, a pixel defining layer, a light-emitting layer and a cathode.

7. The method according to claim 6 , wherein setting the groove in the bonding region of the display substrate comprises:
directly forming the insulating layer having the groove as manufacturing the insulating layer.

8. The method according to claim 7 , wherein directly forming the insulating layer having the groove as manufacturing the insulating layer comprises:
removing a portion of the second insulating layer between at least two adjacent pads as patterning the second insulating layer and removing a portion of the interlayer insulating layer between at least two adjacent pads as patterning the interlayer insulating layer, or
simultaneously removing a portion of the second insulating layer and interlayer insulating layer between at least two adjacent pads as patterning the interlayer insulating layer.

9. The method according to claim 8 , wherein directly forming the insulating layer having the groove as manufacturing the insulating layer further comprises:
simultaneously removing a portion of the buffer layer between at least two adjacent pads as patterning the buffer layer; and simultaneously removing a portion of the first insulating layer between at least two adjacent pads as patterning the first insulating layer; or
simultaneously removing a portion of the buffer layer and the first insulating layer between at least two adjacent pads as patterning the first insulating layer.

10. A display panel, comprising: a display substrate;
wherein,
the display substrate comprises: a bonding region; a plurality of pads at intervals in the bonding region; and an insulating layer for spacing apart the pads, wherein a groove is in the insulating layer between at least two adjacent pads; and
wherein,
the display substrate further comprises: a base substrate, an active layer, a first metal layer, a second metal layer, a drain/source metal layer, a flat layer, an anode, a pixel defining layer, a light-emitting layer and a cathode;
the insulating layer comprises a buffer layer, a first insulating layer, a second insulating layer, and an interlayer insulating layer;
the buffer layer, the active layer, the first insulating layer, the first metal layer, the second insulating layer, the second metal layer, the interlayer insulating layer, the source/drain metal layer, the flat layer, the anode, the pixel defining layer, the light-emitting layer, and the cathode are sequentially on the base substrate; and
a depth of the groove is no less than a sum of thicknesses of the second insulating layer and the interlayer insulating layer.

11. The display panel according to claim 10 , wherein the groove is between any two adjacent pads.

12. The display panel according to claim 10 , wherein the pads comprise input pads and output pads, and the bonding region comprises a first region and a second region at intervals, wherein the input pads are in the first region, the output pads are in the second region, and the groove is set between the first region and the second region.

13. The display panel according to claim 10 , wherein a depth of the groove is no less than a thickness of an uppermost sub-insulating layer among the plurality of sub-insulating layers, and the uppermost sub-insulating layer is a sub-insulating layer farthest from the base substrate.

14. A display device, comprising the display panel of claim 10 .

15. The display panel according to claim 10 , wherein a depth of the groove is equal to a thickness of the insulating layer.

16. A display substrate, comprising:
a base substrate;
at least one insulating layer on a side of the base substrate;
a first pad array on a side of the at least one insulating layer away from the base substrate;
a second pad array on the side of the at least one insulating layer away from the base substrate;
a groove in the at least one insulating layer between the first pad array and the second pad array;
wherein the display substrate comprises a display region and a bonding region on a side of the display region;
the first pad array and the second pad array are both in the bonding region, and the first pad array is closer to the display region relative to the second pad array; and
the groove is configured to accommodate an overflow anisotropic conductive film during a bonding process; and
wherein,
the display substrate further comprising: an active layer, a first metal layer, a second metal layer, a drain/source metal layer, a flat layer, an anode, a pixel defining layer, a light-emitting layer and a cathode;
the insulating layer comprises a buffer layer, a first insulating layer, a second insulating layer, and an interlayer insulating layer;
the buffer layer, the active layer, the first insulating layer, the first metal layer, the second insulating layer, the second metal layer, the interlayer insulating layer, the source/drain metal layer, the flat layer, the anode, the pixel defining layer, the light-emitting layer, and the cathode are sequentially on the base substrate; and
a depth of the groove is no less than a sum of t

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Xin Yanxia
• Yang Zhiyong
• Chen Fei

Classifications

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K50/80

  Constructional details · CPC title

• H10K59/124 Primary

  Insulating layers formed between TFT elements and OLED elements · CPC title

• H01L51/56

  Electricity · mapped topic

• H01L51/52 Primary

  Electricity · mapped topic