Recovering from failure in programming a nonvolatile memory

Patent metadata

Field	Value
Publication number	US-10762967-B2
Application number	US-201816202130-A
Country	US
Kind code	B2
Filing date	Nov 28, 2018
Priority date	Jun 28, 2018
Publication date	Sep 1, 2020
Grant date	Sep 1, 2020

Abstract

A controller includes an interface and a processor. The interface is configured to communicate with a nonvolatile memory including multiple memory cells organized in multiple memory blocks that each includes multiple Word Lines (WLs). The processor is configured to store first data in one or more WLs of a memory block, the first data occupies less than a maximal number of WLs available in the memory block, to calculate redundancy data over the first data and store the redundancy data in a dedicated memory, to program second data to a selected WL of the memory block that was not programmed with the first data, to check a programming status resulting from the programming of the selected WL, and in response to identifying that programming the second data to the selected WL has corrupted at least part of the first data, to recover the first data using the redundancy data.

First claim

The invention claimed is:

1. A controller, comprising:
an interface, which is configured to communicate with a nonvolatile memory comprising multiple memory cells organized in multiple memory blocks, wherein each memory block comprises multiple Word Lines (WLs) of the memory cells; and
a processor, configured to:
receive first data, and store the first data in one or more WLs of a given memory block, wherein the first data occupies less than a maximal number of WLs available in the given memory block;
calculate redundancy data over the first data, and store the redundancy data in a dedicated memory;
receive second data and program the second data to a selected WL of the given memory block that was not programmed with the first data;
check a programming status resulting from the programming of the selected WL;
in response to identifying that programming the second data to the selected WL has corrupted at least part of the first data, recover the first data using the redundancy data; and
in response to identifying that programming the second data has filled the given memory block completely, calculate for the given memory block permanent redundancy data, smaller than the redundancy data, and store the permanent redundancy data in the nonvolatile memory.

2. The controller according to claim 1 , wherein in response to identifying that the second data has been programmed successfully and that programming the second data has filled the given memory block completely, the processor is configured to discard the redundancy data from the dedicated memory.

3. The controller according to claim 1 , wherein the processor is configured to identify that programming the second data has corrupted the first data by receiving a program failure indication from the nonvolatile memory.

4. The controller according to claim 1 , wherein the processor is configured to identify that programming the second data has corrupted the first data by reading and verifying the first data.

5. The controller according to claim 1 , wherein the memory blocks support programming a first number of bits per memory cell, wherein the dedicated memory comprises one or more selected memory blocks in the nonvolatile memory, and wherein the processor is configured to program the redundancy data to the one or more selected memory blocks using a second number of bits per memory cell smaller than or equal to the first number.

6. The controller according to claim 1 , wherein the dedicated memory comprises an auxiliary nonvolatile memory, which resides externally to the nonvolatile memory and is accessible to the controller.

7. The controller according to claim 1 , wherein the dedicated memory comprises an auxiliary volatile memory, wherein the processor is configured to recover the redundancy data after system power is lost and then resumes, by recovering the redundancy data based on the first data, and storing the recovered redundancy data in the volatile memory.

8. The controller according to claim 1 , wherein the memory blocks are organized in multiple planes whose WLs are accessible in parallel, and wherein the processor is configured to calculate multiple plane-specific redundancy chunks for respective memory blocks belonging to different respective planes.

9. The controller according to claim 8 , wherein the processor is configured to recover a WL whose programming to multiple memory blocks in multiple respective planes has failed, using the multiple plane-specific redundancy chunks.

10. The controller according to claim 1 , wherein the processor is configured to calculate the redundancy data by applying bit-wise XOR operations among WLs programmed with the first data, and to calculate the permanent redundancy data by applying bit-wise XOR operations over the redundancy data.

11. The controller according to claim 1 , wherein the processor is configured to calculate the permanent redundancy data from the redundancy data by reading at least part of the first data from the memory block, and applying ECC encoding to the redundancy data and to the at least part of the first data that was read.

12. The controller according to claim 1 , wherein the processor is configured to allocate at least a portion of a storage space of the dedicated memory from a predefined pool of multiple spare memory blocks.

13. The controller according to claim 1 , wherein the dedicated memory comprises the nonvolatile memory or an auxiliary memory accessible to the controller, wherein the processor is configured to select a memory for storing the redundancy data, between the nonvolatile memory and the auxiliary memory, and to store the redundancy data in the selected memory.

14. The controller according to claim 13 , wherein the controller and the nonvolatile memory are comprised in a storage system, wherein the processor is configured to select the memory for storing the redundancy data, at power up, based on a configuration of the storage system.

15. The controller according to claim 13 , wherein the processor is configured to select the memory for storing the redundancy data based on a criterion that aims to maximize at least one of (i) a writing throughput to the nonvolatile memory and (ii) a number of programming and erasure cycles that the nonvolatile memory sustains.

16. The controller according to claim 13 , wherein the processor is configured to move at least some of redundancy data previously written to one of the nonvolatile memory and the auxiliary memory to the other one of the nonvolatile memory and the auxiliary memory, based on evaluating storage space availability in at least one of the nonvolatile memory and the auxiliary memory.

17. The controller according to claim 13 , wherein the processor is configured to hold a table for translating between logical addresses used by a host coupled to the controller and physical addresses used by the nonvolatile memory, to check a fragmentation level of the table, and in response to detecting that the fragmentation level exceeds a predefined fragmentation threshold, to select the nonvolatile memory for storing the redundancy data.

18. The controller according to claim 13 , wherein the processor is configured to allocate in the auxiliary memory a given storage space to be shared between (i) a write buffer for storing data pending programming to the nonvolatile memory and (ii) a storage area for storing redundancy data, to estimate a writing rate to the write buffer, and to re-allocate the write buffer and the storage area, based on the estimated writing rate.

19. A method for data storage, comprising:
in a controller that communicates with a nonvolatile memory comprising multiple memory cells organized in multiple memory blocks, wherein each memory block comprises multiple Word Lines (WLs) of the memory cells,
receiving first data, and storing the first data in one or more WLs of a given memory block, wherein the first data occupies less than a maximal number of WLs available in the given memory block;
calculating redundancy data over the first data, and storing the redundancy data in a dedicated memory;

receiving second data and programming the second data to a selected WL of the given memory block that was not programmed with the first data;
checking a programming status resulting from the programming of the selected WL;
in response to identifying that programming the second data to the selected WL has corrupted at least part of the first data, recovering the first data using the redundancy data; and
in response to identifying that programming the se

Assignees

• Apple Inc

Inventors

• Shappir Assaf
• Baum Barak
• Sagron Itay
• Guy Roman
• Ben-Yehuda Guy
• Mouler Stas

Classifications

• G06F11/108

  Parity data distribution in semiconductor storages, e.g. in SSD · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C2029/1202

  Word line control · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title