Apparatuses, methods, and systems for blockchain transaction acceleration

Patent metadata

Field	Value
Publication number	US-10761877-B2
Application number	US-201815884259-A
Country	US
Kind code	B2
Filing date	Jan 30, 2018
Priority date	Jul 21, 2017
Publication date	Sep 1, 2020
Grant date	Sep 1, 2020

Abstract

Methods and apparatuses relating to accelerating blockchain transactions are described. In one embodiment, a processor includes a hardware accelerator to execute an operation of a blockchain transaction, and the hardware accelerator includes a dispatcher circuit to route the operation to a transaction processing circuit when the operation is a transaction operation and route the operation to a block processing circuit when the operation is a block operation. In another embodiment, a processor includes a hardware accelerator to execute an operation of a blockchain transaction; and a network interface controller including a dispatcher circuit to route the operation to a transaction processing circuit of the hardware accelerator when the operation is a transaction operation and route the operation to a block processing circuit of the hardware accelerator when the operation is a block operation.

First claim

What is claimed is:

1. An apparatus comprising:
a core to execute a thread and offload an operation of a blockchain transaction;
a transaction processing circuit of a hardware accelerator to execute an offloaded operation of a blockchain transaction;
a block processing circuit of the hardware accelerator to execute an offloaded operation of a blockchain transaction; and
a dispatcher circuit of the hardware accelerator to route an offloaded operation to a controller of the transaction processing circuit of the hardware accelerator when the offloaded operation is a transaction operation and route the offloaded operation to a controller of the block processing circuit of the hardware accelerator when the offloaded operation is a block operation, wherein the controller of the transaction processing circuit is to determine a compute circuit block of a plurality of different types of compute blocks of the transaction processing circuit to be used and send the transaction operation to the compute circuit block if available and to the core if not available, and the controller of the block processing circuit is to determine a compute circuit block of a plurality of different types of compute blocks of the block processing circuit to be used and send the block operation to the compute circuit block if available and to the core if not available.

2. The apparatus of claim 1 , wherein the dispatcher circuit is to perform an initial processing for the offloaded operation before routing the offloaded operation, and the initial processing comprises a digital signature operation.

3. The apparatus of claim 1 , wherein the dispatcher circuit is to route the offloaded operation to a peer processing circuit when the offloaded operation is a peer operation.

4. The apparatus of claim 3 , wherein the peer operation is a request for a missing transaction of a block from peers.

5. The apparatus of claim 3 , wherein the peer operation is to cause the peer processing circuit to send a missing transaction of a block to peers.

6. The apparatus of claim 3 , wherein the transaction processing circuit comprises a dependency checker to check a transaction of the transaction operation for dependent transactions, and cause the peer processing circuit to retrieve any missing dependent transactions.

7. A method comprising:
offloading an operation from a hardware processor to a hardware accelerator;
routing the operation with a dispatcher circuit to a controller of a transaction processing circuit of the hardware accelerator when the operation is a transaction operation;
routing the operation with the dispatcher circuit to a controller of a block processing circuit of the hardware accelerator when the operation is a block operation;
determining, by the controller of the transaction processing circuit, a compute circuit block of a plurality of different types of compute blocks of the transaction processing circuit to be used;
sending the transaction operation to the compute circuit block of the transaction processing circuit if available and to the hardware processor if not available;
determining, by the controller of the block processing circuit, a compute circuit block of a plurality of different types of compute blocks of the block processing circuit to be used;
sending the block operation to the compute circuit block of the block processing circuit if available and to the hardware processor if not available;
performing the routed operation with the compute circuit block of the transaction processing circuit of the hardware accelerator when the operation is the transaction operation and the compute circuit block of the transaction processing circuit is available; and
performing the routed operation with the compute circuit block of the block processing circuit of the hardware accelerator when the operation is the block operation and the compute circuit block of the block processing circuit is available.

8. The method of claim 7 , further comprising performing an initial processing for the operation with the dispatcher circuit before routing the operation, wherein the initial processing comprises a digital signature operation.

9. The method of claim 7 , further comprising routing the operation with the dispatcher circuit to a peer processing circuit of the hardware accelerator when the operation is a peer operation; and performing the routed operation with the peer processing circuit of the hardware accelerator when the operation is the peer operation.

10. The method of claim 9 , wherein the peer operation comprises requesting a missing transaction of a block from peers.

11. The method of claim 9 , wherein the peer operation comprises sending a missing transaction of a block to peers.

12. The method of claim 9 , further comprising checking a transaction of the transaction operation for dependent transactions with a dependency checker of the transaction processing circuit, and the dependency checker causing the peer processing circuit to retrieve any missing dependent transactions.

13. An apparatus comprising:
a transaction processing circuit of a hardware accelerator to execute an operation of a blockchain transaction;
a block processing circuit of the hardware accelerator to execute an operation of a blockchain transaction; and
a network interface controller comprising a dispatcher circuit to route an operation to a controller of the transaction processing circuit of the hardware accelerator when the operation is a transaction operation and route the operation to a controller of the block processing circuit of the hardware accelerator when the operation is a block operation, wherein the controller of the transaction processing circuit is to determine a compute circuit block of a plurality of different types of compute blocks of the transaction processing circuit to be used and send the transaction operation to the compute circuit block if available and from the transaction processing circuit if not available, and the controller of the block processing circuit is to determine a compute circuit block of a plurality of different types of compute blocks of the block processing circuit to be used and send the block operation to the compute circuit block if available and from the block processing circuit if not available.

14. The apparatus of claim 13 , wherein the dispatcher circuit is to perform an initial processing for the operation before routing the operation, and the initial processing comprises a digital signature operation.

15. The apparatus of claim 13 , wherein the dispatcher circuit is to route the operation to a peer processing circuit when the operation is a peer operation.

16. The apparatus of claim 15 , wherein the peer operation is a request for a missing transaction of a block from peers.

17. The apparatus of claim 15 , wherein the peer operation is to cause the peer processing circuit to send a missing transaction of a block to peers.

18. The apparatus of claim 15 , wherein the transaction processing circuit comprises a dependency checker to check a transaction of the transaction operation for dependent transactions, and cause the peer processing circuit to retrieve any missing dependent transactions.

19. A method comprising:
receiving an operation for a hardware accelerator with a network interface controller;
routing the operation with a dispatcher circuit of the network interface controller to a controller of a transaction processing circuit of the hardware accelerator when the operation is a transaction operation;
routing the operation with the di

Assignees

• Intel Corp

Inventors

• Peffers Simon N
• Gulley Sean M

Classifications

• G06F9/5044 Primary

  considering hardware capabilities · CPC title

• G06F2209/509

  Offload · CPC title

• G06F9/5027 Primary

  the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title

• H04L9/0894

  Escrow, recovery or storing of secret information, e.g. secret key escrow or cryptographic key storage · CPC title

• H04L9/3252

  using DSA or related signature schemes, e.g. elliptic based signatures, ElGamal or Schnorr schemes · CPC title