Transition timing and training stage operation

Patent metadata

Field	Value
Publication number	US-10756882-B2
Application number	US-201916544776-A
Country	US
Kind code	B2
Filing date	Aug 19, 2019
Priority date	Jun 11, 2015
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

A primary device implementing the subject system of link establishment for single pair Ethernet may include at least one processor. The at least one processor may be configured to transmit a first synchronization sequence to a secondary device, detect a second synchronization sequence transmitted by the secondary device, the second synchronization sequence differing from the first synchronization sequence, and after detection of the second synchronization sequence, initiate a training stage, the train stage comprising exchanging training frames with the secondary device. The at least one processor may be further configured to enter a data mode for data transmissions after completion of the training stage, the data transmissions being distinct from the training frames. In the data mode, data may be forward error correction encoded and then scrambled.

First claim

What is claimed is:

1. A device comprising:
a memory; and
at least one processor configured to:
initiate a timer for a predetermined amount of time;
upon expiration of the timer, transition to a training state; and
responsive to transitioning to the training state, transmit a message to a link partner, the message comprising a twelve octet infofield that includes a scrambler seed value used for scrambler initialization, wherein a last two octets of the twelve octet infofield comprise a CRC value.

2. The device of claim 1 , wherein at least two octets of the twelve octet infofield comprise the scrambler seed value.

3. The device of claim 1 , wherein the CRC value comprises CRC16 value.

4. The device of claim 1 , wherein the at least one processor is further configured to:
transition to a data mode after completing of the training state.

5. The device of claim 1 , wherein a frame format for the training state comprises 2700 pulse amplitude modulation symbols.

6. The device of claim 1 , wherein the at least one processor is further configured to transmit the message by:
appending a header to 80-bit data blocks to produce 81-bit data blocks;
aggregating forty-five 81-bit data blocks and a 9-bit operations, administration and maintenance block to form a forward error correction payload; and
generating one or more forward error correction frames from the forward error correction payload, the one or more forward error correction frames comprising forward error correction symbols.

7. The device of claim 6 , wherein the at least one processor is further configured to transmit the message by:
scrambling the forward error correction symbols to generate scrambled data blocks; and
mapping bits of the scrambled data blocks to ternary symbols.

8. The device of claim 1 , wherein the scrambler initialization comprises a data mode scrambler initialization.

9. A device comprising:
a memory; and
at least one processor configured to:
initiate a timer for a predetermined amount of time;
upon expiration of the timer, transition to a training state; and
responsive to transitioning to the training state, transmit a message to a link partner, the message comprising a twelve octet infofield that includes a scrambler seed value used for data mode scrambler initialization, wherein at least a last two octets of the twelve octet infofield comprise a CRC16 value.

10. The device of claim 9 , wherein at least two octets of the twelve octet infofield comprise the scrambler seed value.

11. The device of claim 9 , wherein the at least one processor is further configured to:
transition to a data mode after completing of the training state.

12. The device of claim 9 , wherein a frame format for the training state comprises 2700 pulse amplitude modulation symbols.

13. The device of claim 9 , wherein the at least one processor is further configured to transmit the message by:
appending a header to 80-bit data blocks to produce 81-bit data blocks;
aggregating forty-five 81-bit data blocks and a 9-bit operations, administration and maintenance block to form a forward error correction payload; and
generating one or more forward error correction frames from the forward error correction payload, the one or more forward error correction frames comprising forward error correction symbols.

14. The device of claim 13 , wherein the at least one processor is further configured to transmit the message by:
scrambling the forward error correction symbols to generate scrambled data blocks; and
mapping bits of the scrambled data blocks to ternary symbols.

15. A method comprising:
receiving a message from a link partner, the message comprising a twelve octet infofield that includes a scrambler seed value;
initializing a descrambler based on the scrambler seed value; and
transitioning to a training state after initializing the descrambler, wherein a last two octets of the twelve octet infofield comprise a CRC16 value.

16. The method of claim 15 , wherein at least two octets of the twelve octet infofield comprise the scrambler seed value.

17. The method of claim 15 , further comprising:
transitioning to a data mode after completing of the training state.

18. The method of claim 15 , wherein a frame format for the training state comprises 2700 pulse amplitude modulation symbols.

Assignees

• Avago Tech Int Sales Pte Lid

Inventors

• Tu Chung Ming
• Wang Peiqing
• Chini Ahmad
• Chen Yencheng
• Tazebay Mehmet Vakif
• Shen Bazhong

Classifications

• H04L12/413

  with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD] · CPC title

• H04L7/048

  using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal · CPC title

• H04L7/10 Primary

  Arrangements for initial synchronisation · CPC title