Circuit device, vibration device, electronic apparatus, and vehicle

US10756752B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10756752-B2
Application numberUS-201816227494-A
CountryUS
Kind codeB2
Filing dateDec 20, 2018
Priority dateDec 28, 2017
Publication dateAug 25, 2020
Grant dateAug 25, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A circuit device includes a selector to which first to n-th voltages are input, an A/D converter circuit to which output voltages of the selector are input as input voltages, and first to n-th quantization error hold circuits that hold charges corresponding to quantization errors in A/D conversion of the first to n-th voltages. The A/D converter circuit performs A/D conversion of an input voltage by a successive approximation operation using a charge redistribution type D/A converter circuit and performs k-th A/D conversion on an i-th voltage by using a charge held in an i-th quantization error hold circuit in (k−1)th A/D conversion of the i-th voltage to output A/D conversion result data DOUT in which the quantization error is noise-shaped.

First claim

Opening claim text (preview).

What is claimed is: 1. A circuit device comprising: a selector that receives first to n-th voltages, n being an integer of 2 or more; an A/D converter circuit that includes a charge redistribution type D/A converter circuit and receives an output voltage of the selector as an input voltage to perform A/D conversion of the input voltage by a successive approximation operation using the D/A converter circuit; and first to n-th quantization error hold circuits that hold charges corresponding to quantization errors in the A/D conversion of the first to n-th voltages, wherein the A/D converter circuit uses a charge held in an i-th quantization error hold circuit as a charge corresponding to a quantization error in (k−1)th A/D conversion of an i-th voltage to perform k-th A/D conversion on the i-th voltage, and outputs A/D conversion result data in which the quantization error is noise-shaped, wherein k is an integer of 2 or more and i is an integer from 1 to n. 2. The circuit device according to claim 1 , wherein the A/D converter circuit includes an adder circuit that outputs a voltage obtained by subtracting a voltage corresponding to the charges held in the i-th quantization error hold circuit from a voltage corresponding to the input voltage, the D/A converter circuit outputs a differential voltage between the output voltage of the adder circuit and the D/A converted voltage of successive approximation data, and the i-th quantization error hold circuit holds a charge corresponding to the differential voltage after the successive approximation operation for the i-th voltage is completed. 3. The circuit device according to claim 2 , wherein the A/D converter circuit includes a comparator circuit that makes a comparison determination between the output voltage of the adder circuit and the D/A converted voltage of the successive approximation data based on the differential voltage from the D/A converter circuit, and a control circuit that updates the successive approximation data based on the comparison result by the comparator circuit to output the successive approximation data to the D/A converter circuit. 4. The circuit device according to claim 2 , wherein the D/A converter circuit is a differential D/A converter circuit including a capacitor array circuit on a positive electrode side and a capacitor array circuit on a negative electrode side, the adder circuit includes a fully differential operational amplifier, a feedback capacitor on the positive electrode side that is provided between an inverting output node and a non-inverting input node of the operational amplifier, and a feedback capacitor on the negative electrode side that is provided between a non-inverting output node and an inverting input node of the operational amplifier, the i-th quantization error hold circuit includes a hold circuit on the positive electrode side and a hold circuit on the negative electrode side, the hold circuit on the positive electrode side includes a hold capacitor on the positive electrode side, a first switch on the positive electrode side that connects one end of the hold capacitor on the positive electrode side to any one of a sampling node of the capacitor array on the positive electrode side and a node of a common voltage, and a second switch on the positive electrode side that connects the other end of the hold capacitor on the positive electrode side to any one of the node of the common voltage and the inverting input node, and the hold circuit on the negative electrode side includes a hold capacitor on the negative electrode side, a first switch on the negative electrode side that connects one end of the hold capacitor on the negative electrode side to any one of a sampling node of the capacitor array on the negative electrode side and the node of the common voltage, and a second switch on the negative electrode side that connects the other end of the hold capacitor on the negative electrode side to any one of the node of the common voltage and the non-inverting input node. 5. The circuit device according to claim 2 , wherein the adder circuit includes a fully differential operational amplifier, a chopping modulation circuit that performs chopping modulation on voltages input to a non-inverting input node and an inverting input node of the operational amplifier, and a chopping demodulation circuit that performs chopping demodulation on voltages output from the inverting output node and the non-inverting output node of the operational amplifier. 6. The circuit device according to claim 1 , further comprising: a processing circuit that outputs frequency control data based on the A/D conversion result data corresponding to the input voltage which is a temperature detection voltage; and an oscillation signal generator circuit that generates an oscillation signal of an oscillation frequency corresponding to the frequency control data by using a vibrator. 7. The circuit device according to claim 1 , wherein first to m-th temperature detection voltages from first to m-th temperature sensors (m is an integer from 1 to n) are input to the selector as first to m-th voltages of the first to n-th voltages. 8. A vibration device comprising: the circuit device according to claim 1 ; and a vibrator that is connected to the circuit device. 9. The vibration device according to 8 , further comprising: first to m-th temperature sensors (m is an integer of 1 to n), wherein first to m-th temperature detection voltages from the first to m-th temperature sensors are input to the selector as first to m-th voltages of the first to n-th voltages. 10. An electronic apparatus comprising: the circuit device according to claim 1 . 11. A vehicle comprising: the circuit device according to claim 1 .

Assignees

Inventors

Classifications

  • H03M3/426Primary

    the quantiser being a successive approximation type analogue/digital converter · CPC title

  • using time-division multiplexing · CPC title

  • the FBC comprising one or more capacitors, not being switched capacitors, and being coupled between the LC and the IC · CPC title

  • using IC blocks as the active amplifying circuit · CPC title

  • with charge redistribution · CPC title

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What does patent US10756752B2 cover?
A circuit device includes a selector to which first to n-th voltages are input, an A/D converter circuit to which output voltages of the selector are input as input voltages, and first to n-th quantization error hold circuits that hold charges corresponding to quantization errors in A/D conversion of the first to n-th voltages. The A/D converter circuit performs A/D conversion of an input volta…
Who is the assignee on this patent?
Seiko Epson Corp
What technology area does this patent fall under?
Primary CPC classification H03M3/426. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 25 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).