Method of manufacturing an OLED panel and an OLED panel

US10756292B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10756292-B2
Application numberUS-201715742517-A
CountryUS
Kind codeB2
Filing dateNov 29, 2017
Priority dateOct 13, 2017
Publication dateAug 25, 2020
Grant dateAug 25, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of manufacturing an OLED panel and an OLED panel are provided. The method includes forming an anode connected to a source of a TFT, and a strap electrode connected to an auxiliary electrode on a TFT substrate. A sharp shaped corner is formed on the strap electrode, therefore an area of the electron transport layer and the electron injection layer corresponding to the sharp shaped corner have a thinner thickness. By applying a voltage between the auxiliary electrode and the cathode, the electron transport layer and the electron injection layer corresponding to the sharp shaped corner are punctured, the cathode is directly connected to the strap electrode and further conducted to the auxiliary electrode, resulting in a signal is inputted to the cathode through the auxiliary electrode during display. The problem of uneven display of the OLED panel due to the IR drop of the cathode is improved.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of manufacturing an OLED panel, comprising the following steps: step S 1 , providing a TFT substrate; the substrate comprising a base substrate, a TFT and an auxiliary electrode disposed on the base substrate at intervals, the TFT having a source electrode; step S 2 , patterning a planarization layer formed on the TFT and the auxiliary electrode, forming a first via hole and a second via hole on the planarization layer exposing the source electrode and the auxiliary electrode, respectively; step S 3 , forming an anode and a strap electrode directly on the planarization layer at intervals; the anode and the strap electrode being in contacted with the planarization layer; the anode being connected to the source electrode through the first via hole, the strap electrode being connected to the auxiliary electrode through the second via hole, the strap electrode being formed with a sharp shaped corner; step S 4 , forming a pixel defining layer on the planarization layer, the anode, and the strap electrode, the pixel defining layer being provided with a first opening exposing the anode, and the pixel defining layer exposing an area of the sharp shaped corner of the strap electrode; step S 5 , sequentially forming a hole injection layer, a hole transport layer and a light-emitting layer on the anode in the first opening; and sequentially forming an electron transport layer, an electron injection layer and a cathode on the light-emitting layer, the pixel definition layer and the strap electrode, wherein the sharp shaped corner of the strap electrode is in a state of being spaced from the cathode by the electron transport layer and the electron injection layer, the electron transport layer and the electron injection layer corresponding to the area of the sharp shaped corner have a thinner thickness; step S 6 , applying a voltage between the auxiliary electrode and the cathode to generate an electric field between the strap electrode and the cathode, and thereby the electron transport layer and the electron injection layer corresponding to the area of the sharp shaped corner being punctured under the electric field, and the sharp shaped corner being changed from the state of being spaced from the cathode to be a state of being directly connected with the cathode. 2. The method of manufacturing an OLED panel according to claim 1 , wherein a plurality of third via holes are formed on the strap electrode, a tip angle is formed between each side wall of the third via hole and an upper surface of the strap electrode; the pixel defining layer exposes an area where the plurality of third via holes are formed on the strap electrode; in the step S 5 , the electron transport layer, the electron injection layer and the cathode are further formed on the planarization layer exposed from the plurality of third via holes in sequence; in the step S 6 , after a voltage is applied between the auxiliary electrode and the cathode, a portion of the electron transport layer and the electron injection layer corresponding to the tip angle formed between the sidewall of the third via hole and the upper surface of the strap electrode is removed to form a plurality of second openings, and the cathode is connected to the strap electrode through the second opening. 3. The method of manufacturing an OLED panel according to claim 1 , wherein the TFT comprises: an active layer disposed above the base substrate, a gate insulating layer and a gate electrode sequentially disposed on the active layer, an interlayer insulating layer covering the active layer and the gate electrode, and a source electrode and a drain electrode formed on the interlayer insulating layer at intervals; the auxiliary electrode comprises a first sub-auxiliary electrode disposed on the interlayer insulating layer spacing apart from the source electrode and the drain electrode, the second via hole exposes the first sub-auxiliary electrode; the interlayer insulating layer is provided with a fourth via hole and a fifth via hole located above both sides of the active layer, the source electrode and the drain electrode are connected to the both sides of the active layer through the fourth via hole and the fifth via hole; the TFT substrate further comprises a passivation layer covering the interlayer insulating layer, the source electrode, the drain electrode and the first sub-auxiliary electrode, the passivation layer is provided with a seventh via hole and an eighth via hole respectively exposing the source electrode and the first sub-auxiliary electrode; in the step S 2 , the planarization layer is disposed on the passivation layer, the first via hole and the second via hole are respectively located above the seventh via hole and the eighth via hole. 4. The method of manufacturing an OLED panel according to claim 3 , wherein the auxiliary electrode further comprises a second sub-auxiliary electrode disposed on the base substrate; the TFT substrate further comprises: a metal light-shielding layer disposed on the base substrate spacing apart from the second sub-auxiliary electrode, and a buffer layer disposed on the base substrate covering the metal light-shielding layer and the second sub-auxiliary electrode; the active layer is disposed on the buffer layer and correspondingly located above the metal light-shielding layer, the interlayer insulating layer is disposed on the buffer layer covering the active layer and the gate electrode; the buffer layer and the interlayer insulating layer are provided with a sixth via hole exposing the second sub-auxiliary electrode, the first sub-auxiliary electrode is connected to the second sub-auxiliary electrode through the sixth via hole. 5. The method of manufacturing an OLED panel according to claim 2 , wherein the plurality of third via holes are arranged in array, and an opening shape of the plurality of third via holes is a rectangle, a triangle, or a circle. 6. A method of manufacturing an OLED panel, comprising the following steps: step S 1 , providing a TFT substrate; the substrate comprising a base substrate, a TFT and an auxiliary electrode disposed on the base substrate at intervals, the TFT having a source electrode; step S 2 , patterning a planarization layer formed on the TFT substrate, forming a first via hole and a second via hole on the planarization layer exposing the source electrode and the auxiliary electrode, respectively; step S 3 , forming an anode and a strap electrode directly on the planarization layer at intervals; the anode and the strap electrode being in contacted with the planarization layer; the anode being connected to the source electrode through the first via hole, the strap electrode being connected to the auxiliary electrode through the second via hole, the strap electrode being formed with a sharp shaped corner; step S 4 , forming a pixel defining layer on the planarization layer, the anode, and the strap electrode, the pixel defining layer being provided with a first opening exposing the anode, and the pixel defining layer exposing an area of the sharp shaped corner of the strap electrode; step S 5 , sequentially forming a hole injection layer, a hole transport layer and a light-emitting layer on the anode in the first opening; and sequentially forming an electron transport layer, an electron injection layer and a cathode on the light-emitting layer, the pixel definition layer and the strap electrode, wherein the sharp shaped corner of the strap electrode is in a state of being spaced from the cathode by the electron transport layer and the electron injection layer, the electron transport layer and the electron injection layer corresponding to the area of the sharp shaped corner have a thinner thickness; step S 6 , applying a voltage between the auxiliary el

Assignees

Inventors

Classifications

  • combined with auxiliary electrodes · CPC title

  • combined with auxiliary electrodes · CPC title

  • H10D86/441Primary

    Interconnections, e.g. scanning lines · CPC title

  • characterised by the compositions or shapes of the interlayer dielectrics · CPC title

  • comprising manufacture, treatment or coating of substrates · CPC title

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What does patent US10756292B2 cover?
A method of manufacturing an OLED panel and an OLED panel are provided. The method includes forming an anode connected to a source of a TFT, and a strap electrode connected to an auxiliary electrode on a TFT substrate. A sharp shaped corner is formed on the strap electrode, therefore an area of the electron transport layer and the electron injection layer corresponding to the sharp shaped corne…
Who is the assignee on this patent?
Shenzhen China Star Optoelectronics Semiconductor Display Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D86/441. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 25 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).