N-channel gallium nitride transistors

Patent metadata

Field	Value
Publication number	US-10756183-B2
Application number	US-201816041657-A
Country	US
Kind code	B2
Filing date	Jul 20, 2018
Priority date	Dec 18, 2014
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

The present description relates to n-channel gallium nitride transistors which include a recessed gate electrode, wherein the polarization layer between the gate electrode and the gallium nitride layer is less than about 1 nm. In additional embodiments, the n-channel gallium nitride transistors may have an asymmetric configuration, wherein a gate-to drain length is greater than a gate-to-source length. In further embodiment, the n-channel gallium nitride transistors may be utilized in wireless power/charging devices for improved efficiencies, longer transmission distances, and smaller form factors, when compared with wireless power/charging devices using silicon-based transistors.

First claim

What is claimed is:

1. An n-channel gallium nitride transistor, comprising:
a gallium nitride layer;
a source structure and a drain structure formed in the gallium nitride layer;
a charge inducing layer comprising a polarization layer extending between the source structure and the drain structure; and
a gate electrode extending at least partially into the polarization layer, wherein a thickness of a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is less than about 1 nm.

2. The n-channel gallium nitride transistor of claim 1 , further comprising a gate dielectric disposed between the gate electrode and the polarization layer.

3. The n-channel gallium nitride transistor of claim 1 , further comprising a portion of the polarization layer which is not between the gate electrode and the gallium nitride layer is between about 5 nm and 10 nm.

4. The n-channel gallium nitride transistor of claim 1 , wherein the polarization layer is selected from the group consisting of aluminum gallium nitride, aluminum indium nitride, and indium gallium nitride.

5. The n-channel gallium nitride transistor of claim 1 , further including a crystal transition layer disposed between the gallium nitride layer and the polarization layer.

6. The n-channel gallium nitride transistor of claim 5 , wherein the crystal transition layer is selected from the group consisting of indium nitride and aluminum nitride.

7. The n-channel gallium nitride transistor of claim 1 , further including a gate-to-drain length between about 120 nm to about 400 nm and a gate-to-source length between about 5 nm to about 400 nm.

8. The n-channel gallium nitride transistor of claim 7 , wherein the gate-to drain length is greater than the gate-to-source length.

9. A method of forming an n-channel gallium nitride transistor, comprising:
forming a gallium nitride layer;
forming a charge inducing layer comprising a polarization layer on the gallium nitride layer;
forming a source structure and a drain structure formed in the gallium nitride layer;
forming a recess within the polarization layer between the source structure and the drain structure, wherein a thickness of a portion of the polarization layer which is between the recess and the gallium nitride layer is less than about 1 nm;
forming asymmetrical dielectric spacers of different widths;
forming a gate dielectric within the recess; and
forming a gate electrode adjacent the gate dielectric.

10. The method of claim 9 , wherein forming the charge inducing layer comprising the polarization layer on the gallium nitride layer comprises forming the charge inducing layer comprising the polarization layer having a thickness of between about 5 nm and 10 nm.

11. The method of claim 9 , wherein forming the charge inducing layer comprises forming the polarization layer selected from the group consisting of aluminum gallium nitride, aluminum indium nitride, and indium gallium nitride.

12. The method of claim 9 , further including forming a crystal transition layer between the gallium nitride layer and the polarization layer.

13. The method of claim 12 , wherein forming the crystal transition layer comprises forming the crystal transition layer from a material selected from the group consisting of indium nitride and aluminum nitride.

14. The method of claim 9 , further including forming a gate-to-drain length between about 120 nm to about 400 nm and forming a gate-to-source length between about 5 nm to about 400 nm.

15. The method of claim 14 , wherein the gate-to-drain length is greater than the gate-to-source length.

16. A wireless power/charging device transmission module, comprising:
a coil assembly; and
a transmitter, wherein the transmitter includes at least one n-channel gallium nitride transistor, comprising:
a gallium nitride layer;
a source structure and a drain structure formed in the gallium nitride layer;
a charge inducing layer comprising a polarization layer extending between the source structure and the drain structure; and
a gate electrode extending at least partially into the polarization layer.

17. The wireless power/charging device transmission module of claim 16 , wherein a thickness of a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is less than about lnm.

18. The wireless power/charging device transmission module of claim 16 , further comprising a gate dielectric disposed between the gate electrode and the polarization layer.

19. The wireless power/charging device transmission module of claim 16 , further comprising a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is between about 5 nm and 10 nm.

20. The wireless power/charging device transmission module of claim 16 , further including a crystal transition layer disposed between the gallium nitride layer and the polarization layer.

21. A wireless power/charging device receiving module, comprising:
a coil assembly;
a rectifier; and
a load unit including a voltage regulator and a battery, wherein the voltage regulator includes at least one n-channel gallium nitride transistor, comprising:
a gallium nitride layer;
a source structure and a drain structure formed in the gallium nitride layer;
a charge inducing layer comprising a polarization layer extending between the source structure and the drain structure; and
a gate electrode extending at least partially into the polarization layer.

22. The wireless power/charging device receiving module of claim 21 , wherein a thickness of a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is less than about lnm.

23. The wireless power/charging device receiving module of claim 21 , further comprising a gate dielectric disposed between the gate electrode and the polarization layer.

24. The wireless power/charging device receiving module of claim 21 , further comprising a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is between about 5 nm and 10 nm.

25. The wireless power/charging device receiving module of claim 21 , further including a crystal transition layer disposed between the gallium nitride layer and the polarization layer.

Assignees

• Intel Corp

Inventors

• Then Han Wui
• Dasgupta Sansaptak
• Radosavljevic Marko
• Gardner Sanaz K
• Sung Seung Hoon
• Chau Robert S

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D30/015

  of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title

• H10D62/151 Primary

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title