Semiconductor device

Patent metadata

Field	Value
Publication number	US-10756172-B2
Application number	US-201916273398-A
Country	US
Kind code	B2
Filing date	Feb 12, 2019
Priority date	Jul 14, 2017
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

A semiconductor device having a silicon-on-insulator (SOI) structure in which a source region and a drain region extend along a longitudinal direction that is a direction along a longer side of sides facing each other, and are disposed side-by-side in a lateral direction that is a direction perpendicular to the longitudinal direction. In a plan view, a body region extends along the longitudinal direction and is surrounded by a drift region and an insulating region. A space between the insulating region and the body region in the lateral direction becomes narrower from the center to the end of the body region in the longitudinal direction. This achieves high breakdown voltage in the semiconductor device.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor layer above a main face of a semiconductor substrate, with a buried insulating layer disposed between the semiconductor substrate and the semiconductor layer; a body region of a first conductivity type in an upper portion of the semiconductor layer;
a drain region of a second conductivity type in the upper portion of the semiconductor layer and spaced apart from the body region;
a source region of the second conductivity type in a surface of the body region;
a drift region of the second conductivity type between the drain region and the body region in the semiconductor layer;
an insulating region between the body region and the drain region in a surface of the semiconductor layer, the insulating region overlapping with the drift region;
a gate insulating film extending over a portion of the body region up to an edge of the insulating region in a surface of the semiconductor layer;
a gate electrode extending over a portion of the gate insulating film and a portion of the insulating region; and
an electrode on the source region and an electrode on the drain region, wherein
in a plan view:
the source region and the drain region extend along a longitudinal direction and are disposed side-by-side in a lateral direction, the longitudinal direction being a direction along a longer side of sides facing each other, the lateral direction being a direction perpendicular to the longitudinal direction; and
the body region extends along the longitudinal direction and is surrounded by the drift region and the insulating region,

a space in the lateral direction between the insulating region and the body region becomes narrower from a center to an end of the body region in the longitudinal direction.

2. The semiconductor device according to claim 1 , wherein
in the plan view, the space in the lateral direction between the insulating region and the body region becomes narrower from the center to the end of the body region in the longitudinal direction such that the insulating region and the body region come into contact at the end.

3. The semiconductor device according to claim 1 , wherein
in the plan view, from the center to the end of the body region in the longitudinal direction, the space in the lateral direction between the insulating region and the body region becomes narrower by a width becoming narrower, the width being a width of an uncovered region of the insulating region.

4. The semiconductor device according to claim 1 , wherein
in the plan view, a span of the gate electrode having a ring shape is narrower in the longitudinal direction than in the lateral direction.

5. The semiconductor device according to claim 1 , wherein
in the plan view, a space of a region, which uncovers the body region, of the gate electrode is narrower in the longitudinal direction at the curved portions of the second edge line indicating the body region than in the lateral direction at the straight portions of the second edge line indicating the body region.

6. A semiconductor device, comprising:
a semiconductor layer above a main face of a semiconductor substrate, with a buried insulating layer disposed between the semiconductor substrate and the semiconductor layer;
a body region of a first conductivity type in an upper portion of the semiconductor layer;
a drain region of a second conductivity type in the upper portion of the semiconductor layer and spaced apart from the body region;
a source region of the second conductivity type in a surface of the body region;
a drift region of the second conductivity type between the drain region and the body region in the semiconductor layer;
an insulating region between the body region and the drain region in a surface of the semiconductor layer;
a gate insulating film extending over a portion of the body region up to an edge of the insulating region in a surface of the semiconductor layer;
a gate electrode extending over a portion of the gate insulating film and a portion of the insulating region; and
an electrode on the source region and an electrode on the drain region, wherein
in a plan view:
the source region and the drain region extend along a longitudinal direction and are disposed side-by-side in a lateral direction, the longitudinal direction being a direction along a longer side of sides facing each other, the lateral direction being a direction perpendicular to the longitudinal direction; and
the body region and the insulating region extend along the longitudinal direction and are disposed such that one of the body region and the insulating region surrounds the other of the body region and the insulating region in a layout, the layout including a first edge line which indicates an edge of the insulating region and a second edge line which indicates an edge of the body region, the first edge line and the second edge line passing beneath the gate electrode,

the second edge line forms a boundary between the body region and the semiconductor layer which have impurity concentrations or conductivity types different from each other, and
in the plan view:
the first edge line and the second edge line each have: straight portions that face each other and extend along the longitudinal direction; and curved portions each connecting ends of the straight portions either by a polygonal line forming an obtuse vertex angle or a curved line including an arc;
in the straight portions, the second edge line indicating the body region includes a portion located nearer, in the lateral direction, to the source region than the first edge line indicating the insulating region;
in the curved portions, the first edge line indicating the insulating region includes a portion located nearer, in the longitudinal direction, to the source region than the second edge line indicating the body region;
the first edge line intersects with the second edge line at an intersection; and
at the intersection, an angle made by the first edge line and the second edge line is acute, the first edge line and the second edge line forming a space that becomes narrower in the longitudinal direction.

7. The semiconductor device according to claim 6 , wherein
in the plan view, the angle that is acute at the intersection is in a range from 30 degrees to 60 degrees, inclusive.

8. The semiconductor device according to claim 6 , wherein
in the plan view, in a region in which the body region overlaps with the gate electrode, a space in the longitudinal direction at the curved portions of the second edge line indicating the body region is wider than a space in the lateral direction at the straight portions of the second edge line indicating the body region.

9. The semiconductor device according to claim 6 , wherein
in the plan view, a space, on the gate insulating film, from an edge of the gate electrode to an edge of the insulating region is narrower in the longitudinal direction at the curved portions of the first edge line indicating the insulating region than in the lateral direction at the straight portions of the first edge line indicating the insulating region.

10. The semiconductor device according to claim 6 , wherein
in the plan view, a first end point of a straight portion out of the straight portions of an edge line indicating an edge of the one of the body region and the insulating region is located nearer, in the longitudinal direction, to the source region than a second end point of a straight portion out of the straight portions of an edge line indicating an edge of the other of the body region and the insulating region, the first end point and the second end point being located on a same side of the respectiv

Assignees

• Panasonic Ip Man Co Ltd
• Panasonic Semiconductor Solutions Co Ltd

Inventors

• Ikuta Teruhisa
• Sakurai Hiroshi
• Kanai Satoru

Classifications

• H10D30/603

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title

• H10D30/6717

  the source and the drain regions being asymmetrical · CPC title

• H10D30/6711

  by using electrodes contacting the supplementary regions or layers · CPC title

• H10D30/0281

  of lateral DMOS [LDMOS] FETs · CPC title