Array substrate, manufacturing method thereof and display device

Patent metadata

Field	Value
Publication number	US-10756124-B2
Application number	US-201916407507-A
Country	US
Kind code	B2
Filing date	May 9, 2019
Priority date	Aug 29, 2018
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

An array substrate, manufacturing method thereof, and display device are disclosed. The array substrate includes signal lines; IC connection lines; the IC connection lines include at least two IC connection line groups, the at least two IC connection line groups comprise a first IC connection line group and a second IC connection line group, the array substrate further includes a lead, an orthographic projection of the lead on a straight line in a second direction is overlapped or connected with an orthographic projection of a first IC connection line in the first IC connection line group which is closest to the second IC connection line group on the straight line in a second direction and an orthographic projection of the second IC connection line in the second IC connection line group which is closest to the first IC connection line group on the straight line in a second direction respectively.

First claim

What is claimed is:

1. An array substrate, comprising:
a base substrate;
a plurality of signal lines on the base substrate; and
a plurality of IC connection lines which are arranged in one-to-one correspondence with the plurality of signal lines,
wherein each of the plurality of signal lines extends in a first direction, the plurality of IC connection lines include at least two IC connection line groups arranged in a second direction, the second direction is perpendicular to the first direction, the at least two IC connection line groups are configured to connect the plurality of signal lines to at least two driving ICs,
the at least two IC connection line groups comprise a first IC connection line group and a second IC connection line group which are adjacent to each other, the array substrate further comprises a lead, wherein an orthographic projection of the lead on a straight line in the second direction is overlapped or connected with an orthographic projection of a first IC connection line in the first IC connection line group which is closest to the second IC connection line group on the straight line in the second direction and an orthographic projection of a second IC connection line in the second IC connection line group which is closest to the first IC connection line group on the straight line in the second direction respectively.

2. The array substrate according to claim 1 , wherein the lead is connected with the second IC connection line, and an arrangement order of the signal line corresponding to the first IC connection line and the signal line corresponding to the second IC connection line in the second direction is opposite to an arrangement order of the first IC connection line group and the second IC connection line group in the second direction.

3. The array substrate according to claim 2 , wherein the lead is electrically connected with the signal line corresponding to the second IC connection line through a bridge structure.

4. The array substrate according to claim 3 , wherein the lead is arranged in parallel with the first IC connection line and located on a side of the first IC connection lines away from the plurality of signal lines.

5. The array substrate according to claim 4 , further comprising:
a display area and a peripheral area surrounding the display area; and
a dummy area located on a side of the peripheral area away from the display area,
wherein the plurality of signal lines are located in the display area and the peripheral area, the plurality of IC connection lines are located in the peripheral area, and the dummy area is provided with a mesh structure,
the mesh structure comprises transverse grid lines extending in the first direction and longitudinal grid lines extending in the second direction to form a plurality of openings arranged in an array, and a size of each of the openings crossed by an extension line of a signal line corresponding to the first IC connection line in the second direction is larger than a size of a gap between adjacent ones of the plurality of signal lines in the second direction.

6. The array substrate according to claim 5 , wherein the size of each of the openings crossed by the extension line of the signal line corresponding to the first IC connection line in the second direction is greater than twice of the size of the gap between adjacent ones of the plurality of signal lines in the second direction.

7. The array substrate according to claim 2 , wherein the lead is arranged in parallel with the first IC connection line and located on a side of the first IC connection line away from the plurality of signal lines.

8. The array substrate according to claim 1 , wherein the lead is arranged in parallel with the first IC connection line and located on a side of the first IC connection line away from the plurality of signal lines.

9. The array substrate according to claim 1 , wherein the lead is insulated from the plurality of signal lines and the plurality of IC connection lines.

10. The array substrate according to claim 9 , wherein the lead comprises a first portion parallel to the first IC connection line and a second portion parallel to the second IC connection line.

11. The array substrate according to claim 1 , further comprising:
a display area and a peripheral area surrounding the display area; and
a dummy area located on a side of the peripheral area away from the display area,
wherein the plurality of signal lines are located in the display area and the peripheral area, the plurality of IC connection lines are located in the peripheral area, and the dummy area is provided with a mesh structure,
the mesh structure comprises transverse grid lines extending in the first direction and longitudinal grid lines extending in the second direction to form a plurality of openings arranged in an array, and a size of each of the openings crossed by an extension line of a signal line corresponding to the first IC connection line in the second direction is larger than a size of a gap between adjacent ones of the plurality of signal lines in the second direction.

12. The array substrate according to claim 11 , wherein the size of each of the openings crossed by the extension line of the signal line corresponding to the first IC connection line in the second direction is greater than twice of the size of the gap between adjacent ones of the plurality of signal lines in the second direction.

13. The array substrate according to claim 1 , wherein the plurality of signal lines include gate lines, and the at least two IC connection line groups are configured to connect the gate lines to at least two gate driving ICs.

14. The array substrate according to claim 13 , further comprising:
an anode located on a side of the gate lines away from the base substrate; and
an organic light emitting layer located on a side of the anode away from the base substrate and electrically connected with the anode.

15. The array substrate according to claim 1 , wherein the plurality of signal lines are insulated from each other.

16. A display device, comprising the array substrate according to claim 1 .

17. A manufacturing method of an array substrate, comprising:
forming a conductive layer on a base substrate;
forming a photoresist pattern on a side of the conductive layer away from the substrate; and
performing an etching process by taking the photoresist pattern as a mask to form a plurality of signal lines and a plurality of IC connection lines on the base substrate,
wherein each of the plurality of signal lines extends in a first direction, the plurality of IC connection lines include at least two IC connection line groups arranged in a second direction, the second direction is perpendicular to the first direction, the at least two IC connection line groups are configured to connect the plurality of signal lines to at least two driving ICs,
the at least two IC connection line groups comprise a first IC connection line group and a second IC connection line group which are adjacent to each other, the array substrate further comprises a lead, wherein an orthographic projection of the lead on a straight line in the second direction is overlapped or connected with an orthographic projection of a first IC connection line in the first IC connection line group which is closest to the second IC connection line group on the straight line in the second direction and an orthographic projection of a second IC connection line in the second IC connection line group which is closest to the first IC connection line group on the straight line in

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Song Xingxing
• Cai Zhenfei
• Yu Dayong
• Yu Kun
• Li Zhongzhen
• Wang Wenjie

Classifications

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10D89/00

  Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00 · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title