Loading effect reduction through multiple coat-etch processes

Patent metadata

Field	Value
Publication number	US-10755936-B2
Application number	US-201916396429-A
Country	US
Kind code	B2
Filing date	Apr 26, 2019
Priority date	Dec 31, 2015
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate; and
a first gate, a second gate, and a third gate each disposed over the substrate, the first gate including a first work function metal, the second gate including a second work function metal, and the third gate including a third work function metal;
a dielectric material that separates the first gate, the second gate, and the third gate from one another, wherein the dielectric material includes an interlayer dielectric (ILD) and a gate spacer;
wherein:
the third gate is wider than the first gate and the second gate;
the third work function metal is taller than the first work function metal and the second work function metal; and
the third work function metal and the dielectric material have the same heights.

2. The semiconductor device of claim 1 , wherein the first gate and the third gate are located on opposite sides of the second gate.

3. The semiconductor device of claim 1 , wherein respective widths of the first gate and the second gate vary within 50%-200% of each other.

4. The semiconductor device of claim 1 , wherein the third gate is at least three times wider than either the first gate or the second gate.

5. The semiconductor device of claim 1 , wherein the first work function metal is substantially as tall as the second work function metal.

6. The semiconductor device of claim 1 , wherein the first work function metal is taller than the second work function metal by an amount that is less than 60% of a height of the second work function metal.

7. The semiconductor device of claim 1 , wherein:
the first gate further includes a first fill metal located over the first work function metal;
the second gate further includes a second fill metal located over the second work function metal;
the third gate further includes a third fill metal located over the third work function metal;
at least a portion of the first fill metal is in physical contact with a tallest upper surface of the first work function metal;
at least a portion of the second fill metal is in physical contact with a tallest upper surface of the second work function metal; and
an upper surface of the third fill metal is substantially coplanar with a tallest upper surface of the third work function metal.

8. A semiconductor device, comprising:
a first gate dielectric located over a substrate;
a second gate dielectric located over the substrate, wherein the second gate dielectric is spaced apart from the first gate dielectric;
a third gate dielectric located over the substrate, wherein the third gate dielectric is spaced apart from the first gate dielectric or the second gate dielectric;
a first work function metal located over the first gate dielectric, wherein the first work function metal is substantially shorter than the first gate dielectric;
a second work function metal located over the second gate dielectric, wherein the second work function metal is substantially shorter than the second gate dielectric; and
a third work function metal located over the third gate dielectric, wherein the third work function metal is at least multiple times taller and wider than both the first work function metal and the second work function metal, and wherein the third work function metal and the third gate dielectric have co-planar upper surfaces.

9. The semiconductor device of claim 8 , further comprising:
a first fill metal located over the first work function metal;
a second fill metal located over the second work function metal; and
a third fill metal located over the third work function metal;
wherein:
the third fill metal is wider than the first fill metal and the second fill metal;
the third work function metal and the third gate dielectric have substantially co-planar upper surfaces; and
the first fill metal, the second fill metal, and the third fill metal have substantially coplanar upper surfaces.

10. The semiconductor device of claim 9 , wherein:
the first work function metal defines a first recess;
the second work function metal defines a second recess;
the third work function metal defines a third recess;
a first portion of the first fill metal is located within the first recess but a second portion of the first fill metal is located outside the first recess;
a first portion of the second fill metal is located within the second recess but a second portion of the second fill metal is located outside the second recess; and
an entire portion of the third fill metal is located within the third recess.

11. The semiconductor device of claim 8 , further comprising:
gate spacers disposed on sidewalls of the first gate dielectric, the second gate dielectric, and the third gate dielectric; and
an interlayer dielectric (ILD) disposed between the gate spacers;
wherein the gate spacers and the ILD have the same heights.

12. A semiconductor device, comprising:
a first gate disposed over a substrate, wherein the first gate has a first lateral dimension, and wherein the first gate includes a first work function metal component having a first height;
a second gate disposed over the substrate, wherein the second gate has a second lateral dimension, and wherein the second gate includes a second work function metal component having a second height;
a third gate disposed over the substrate, wherein the third gate has a third lateral dimension, and wherein the third gate includes a third work function metal component having a third height, wherein the third lateral dimension is greater than the first lateral dimension and the second lateral dimension, and wherein the third height is greater than the first height and the second height; and
a dielectric material separating the first gate, the second gate, and the third gate laterally, wherein a height of the dielectric material is substantially greater than the first height and the second height, but is substantially equal to the third height, wherein the dielectric material includes an interlayer dielectric (ILD) and a gate spacer, and wherein the ILD and the gate spacer have co-planar upper surfaces with the third work function metal component but not with the first work function metal component or with the second work function metal component.

13. The semiconductor device of claim 12 , wherein the first height is substantially equal to the second height, and wherein the first lateral dimension is substantially equal to the second lateral dimension.

14. The semiconductor device of claim 12 , wherein the first height is greater than the second height or less than the second height, and wherein the first height differs from the second height by no more than 60%.

15. The semiconductor device of claim 12 , wherein the third lateral dimension exceeds the first lateral dimension or the second lateral dimension by at least a factor of 3.

16. The semiconductor device of claim 12 , wherein:
the first gate includes a first high-k gate dielectric component disposed below the first work function metal component and a first fill metal component disposed over the first work function metal component;
the second gate includes a second high-k gate dielectric component disposed below the second work function metal component and a second fill metal component disposed over the second work function metal component; and
the third gate includes a third high-k gate dielectric component disposed below the third work function metal component and a third fill metal component disposed over the third work function metal component.

17. The semiconductor device of claim 16 , wh

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Jin-Dah
• Shieh Ming-Feng
• Wu Han-Wei
• Lin Yu-Hsien
• Liu Po-Chun
• Chen Stan

Classifications

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10W10/20

  Air gaps · CPC title

• H10W10/021

  of air gaps · CPC title

• H10P14/40 Primary

  of conductive or resistive materials · CPC title