Semiconductor device and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-10755935-B2
Application number	US-201815974476-A
Country	US
Kind code	B2
Filing date	May 8, 2018
Priority date	May 9, 2017
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

A semiconductor device and fabrication method are provided. The method includes providing a first dielectric layer with a first groove on a base substrate. A first gate electrode is formed in the first groove, with a top surface lower than the first dielectric layer. A first protective layer is formed on a portion of the top surface of the first gate electrode, with a first oxygen ionic concentration. A compensating protective layer is formed on a remaining portion of the top surface of the first gate electrode exposed by the first protective layer, with a second oxygen ionic concentration. A second dielectric layer is formed on the first protective layer, on the compensating protective layer, and on the first dielectric layer, with a third oxygen ionic concentration. The first oxygen ionic concentration and second oxygen ionic concentration are smaller than the third oxygen ionic concentration.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a base substrate;
a first dielectric layer on the base substrate, with a first groove through the first dielectric layer and a second groove through the first dielectric layer with an opening smaller than an opening of the first groove;
a first gate electrode in the first groove, with a top surface lower than a top surface of the first dielectric layer;
a second gate electrode in the second groove, with a top surface lower than the top surface of the first dielectric layer;
a first protective layer on a portion of the top surface of the first gate electrode, the first protective layer having a first oxygen ionic concentration;
a second protective layer in the second groove to cover the entire top surface of the second gate electrode;
a compensating protective layer on a remaining portion of the top surface of the first gate electrode exposed by the first protective layer, on the top surface of the first protective layer, on the top surface of the second protective layer and on the top surface of the first dielectric layer, the compensating protective layer having a second oxygen ionic concentration and completely covering the remaining portion of the top surface of the first gate electrode, wherein the compensating protective layer has a protruion going through the first protective layer to be in directly contact with the first gate electrode and the first protective layer; and
a second dielectric layer on the first protective layer, on the second protective layer, on the compensating protective layer and on the first dielectric layer, wherein a material of the second dielectric layer has a third oxygen ionic concentration greater than each of the first oxygen ionic concentration and the second oxygen ionic concentration.

2. The semiconductor device according to claim 1 , wherein:
the first protective layer is made of a material including Si 3 N 4 , SiNO, SiNCO, SiNBO, SiNCBO, or a combination thereof;
the compensating protective layer is made of a material including Si 3 N 4 , SiNO, SiNCO, SiNBO, SiNCBO, or a combination thereof; and
the second dielectric layer is made of a material including SiO 2 .

3. The semiconductor device according to claim 1 , wherein:
the first gate electrode is doped with doping ions including one or more of fluorine ions and chlorine ions.

4. The semiconductor device according to claim 1 , wherein:
the top surface of the first gate electrode includes a central region and an edge region surrounding the central region; and
the first protective layer covers the edge region of the first gate electrode and exposes the central region of the first gate electrode.

5. The semiconductor device according to claim 1 , wherein:
a material of the second protective layer has the first oxygen ionic concentration.

6. The semiconductor device according to claim 5 , wherein:
the second protective layer is made of a material including Si 3 N 4 , SiNO, SiNCO, SiNBO, SiNCBO, or a combination thereof.

7. The semiconductor according to claim 5 , wherein:
the second dielectric layer is located on the top surface of the compensating protective layer.

8. The semiconductor device according to claim 5 , further including:
a first work function layer;
a first gate dielectric layer on the first work function layer;
a second work function layer; and
a second gate dielectric layer on the second work function layer,
wherein:
the first work function layer is located on a bottom and on a portion of the sidewalls of the first groove;
the first work function layer has a top surface coplanar with the top surface of the first gate electrode;
the first gate dielectric layer is located on the bottom of the first groove, and between the base substrate and the first work function layer;
the second work function layer is located on a bottom and on a portion of the sidewalls of the second groove;
the second work function layer has a top surface coplanar with the top surface of the second gate electrode; and
the second gate dielectric layer is located on the bottom of the second groove and between the base substrate and the second work function layer.

9. A method for fabricating a semiconductor device, comprising:
providing a base substrate;
providing a first dielectric layer on the base substrate, the first dielectric layer having a first groove through the first dielectric layer;
forming a second groove through the first dielectric layer with an opening smaller than an opening of the first groove;
forming a first gate electrode in the first groove, with a top surface lower than a top surface of the first dielectric layer;
forming a second gate electrode in the second groove when forming the first gate electrode, wherein the second gate electrode has a top surface lower than the top surface of the first dielectric layer;
forming a first protective layer on a portion of the top surface of the first gate electrode, the first protective layer having a first oxygen ionic concentration;
forming a second protective layer in the second groove to cover the top surface of the second gate electrode;
forming a compensating protective layer on a remaining portion of the top surface of the first gate electrode exposed by the first protective layer, on the top surface of the first protective layer, on the top surface of the second protective layer and on the top surface of the first dielectric layer, the compensating protective layer having a second oxygen ionic concentration, wherein the compensating protective layer has a protruion going through the first protective layer to be in directly contact with the first gate electrode and the first protective layer; and
forming a second dielectric layer on the first protective layer, on the second protective layer, on the compensating protective layer, and on the first dielectric layer, wherein a material of the second dielectric layer has a third oxygen ionic concentration, greater than each of the first oxygen ionic concentration and the second oxygen ionic concentration.

10. The method according to claim 9 , wherein:
the first protective layer is made of a material including Si 3 N 4 , SiNO, SiNCO, SiNBO, SiNCBO, or a combination thereof;
the compensating protective layer is made of a material including Si 3 N 4 , SiNO, SiNCO, SiNBO, SiNCBO, or a combination thereof; and
the second dielectric layer is made of a material including SiO 2 .

11. The method according to claim 9 , wherein:
the first gate electrode is doped with doping ions including one or more of fluorine ions and chlorine ions.

12. The method according to claim 9 , wherein:
a material of the second protective layer has the first oxygen ionic concentration.

13. The method according to claim 12 , wherein the first protective layer is formed by:
forming an initial protective material layer on the top surface of the first gate electrode, on the top surface of the second gate electrode, and on the surface of the first dielectric layer; and
polishing the initial protective material layer by a chemical mechanical polishing process, to expose the central region of the first gate electrode and the top surface of the first dielectric layer, and to form the first protective layer.

14. The method according to claim 12 , wherein the first gate electrode and the second gate electrode are formed by:
forming a gate electrode material layer in the first groove, in the second groove and on the first dielectric layer;
polishing the gate electrode material layer to expose the top surface of the first dielectric layer, and to form the first initial g

Assignees

• Semiconductor Mfg International (Shanghai) Corporation
• Semiconductor Mfg International (Beijing) Corporation

Inventors

• Li Yong

Classifications

• H10P14/6927

  the material being a silicon oxynitride, e.g. SiON or SiON:H · CPC title

• H10P14/6923

  the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG · CPC title

• H10D64/01354 Primary

  passivation or protection of the electrode, e.g. using re-oxidation · CPC title

• H10D84/0144

  Manufacturing their gate insulating layers · CPC title

• H10D84/0142

  the gate conductors having different shapes or dimensions · CPC title