Techniques for multi-read and multi-write of memory circuit

Patent metadata

Field	Value
Publication number	US-10755771-B2
Application number	US-201816226385-A
Country	US
Kind code	B2
Filing date	Dec 19, 2018
Priority date	Dec 19, 2018
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.

First claim

What is claimed is:

1. A circuit comprising:
a memory circuit including a set of memory cells multiplexed with a sense amplifier, the set of memory cells coupled to a same word line; and
a memory controller to:
provide a single assertion of a word line signal on the word line to select the set of memory cells for a multi-read operation; and
sequentially read data from the set of memory cells, using the sense amplifier, based on the single assertion of the word line signal.

2. The circuit of claim 1 , wherein the memory controller is further to precharge bit lines associated with respective memory cells of the set of memory cells prior to the single assertion of the word line signal.

3. The circuit of claim 1 , wherein, to sequentially read the data from the set of memory cells, the memory controller is to:
assert a first read column select signal associated with a first memory cell of the set of memory cells;
enable, responsive to de-assertion of the first read column select signal, the sense amplifier to read a first data bit stored by the first memory cell; and
precharge, responsive to disablement of the sense amplifier, the sense amplifier to prepare the sense amplifier to read a second data bit stored by a second memory cell of the set of memory cells.

4. The circuit of claim 3 , wherein the memory controller is to assert a sense amplifier precharge signal to precharge the sense amplifier, and wherein the memory controller is further to assert a second read column select signal associated with the second memory cell when the precharge signal is de-asserted.

5. The circuit of claim 3 , wherein a combined duration of the assertion of the first read column select signal, the enablement of the sense amplifier, and the precharge of the sense amplifier is one phase of a clock signal associated with the memory circuit.

6. The circuit of claim 3 , wherein the set of memory cells is a first set of memory cells, wherein the memory circuit further includes a second set of memory cells that are multiplexed with the sense amplifier, wherein the second set of memory cells are coupled to a different bit line precharge line than the first set of memory cells, and wherein the memory circuit is to:
precharge bit lines associated with the second set of memory cells while data from the first set of memory cells is being read; and
read data from the second set of memory cells after the precharge of the bit lines associated with the second set of memory cells.

7. The circuit of claim 1 , wherein, to sequentially read the data from the set of memory cells, the memory controller is to read one memory cell per clock phase, and wherein the single assertion of the word line signal has a duration longer than one clock phase.

8. The circuit of claim 1 , wherein, to write data to the set of memory cells, the memory controller is to:
precharge bit lines associated with the set of memory cells;
assert, after the precharge, the word line signal for a time period; and
write data sequentially to the set of memory cells during the time period.

9. The circuit of claim 8 , wherein the set of memory cells is a first set of memory cells, wherein the memory circuit further includes a second set of memory cells that are coupled to a different bit line precharge line than the first set of memory cells, and wherein the memory circuit is to:
precharge bit lines associated with the second set of memory cells while data from the first set of memory cells is being read; and
write data to the second set of memory cells after the precharge of the bit lines associated with the second set of memory cells.

10. The circuit of claim 8 , further comprising an interruptable diode-connected transistor coupled to a first bit line of the bit lines, wherein the diode-connected transistor is to be selectively coupled between the first bit line and a power rail while one or more other memory cells associated with other bit lines are written, and is to be uncoupled while a first memory cell associated with the first bit line is written.

11. The circuit of claim 1 , wherein the set of memory cells includes four memory cells.

12. A circuit comprising:
a memory circuit including a set of memory cells coupled to respective bit lines and a same word line, wherein the bit lines are coupled to a same bit line precharge line; and
a memory controller to:
precharge the bit lines using the bit line precharge line;
assert, after the precharge, a word line signal on the word line for a time period; and
write data sequentially to the set of memory cells during the time period.

13. The circuit of claim 12 , wherein, to write the data sequentially to the set of memory cells, the memory controller is to sequentially assert respective write column select signals while the word line signal remains asserted.

14. The circuit of claim 12 , further comprising an interruptable diode-connected transistor coupled to the bit lines, wherein the diode-connected transistor is to be selectively coupled between a first bit line, of the bit lines, and a power rail while one or more other memory cells associated with other bit lines are written, and is to be uncoupled while a first memory cell associated with the first bit line is written.

15. The circuit of claim 12 , wherein the set of memory cells includes four memory cells.

16. The circuit of claim 12 , wherein the set of memory cells is a first set of memory cells, wherein the memory circuit further includes a second set of memory cells that are coupled to a different bit line precharge line than the first set of memory cells, and wherein the memory circuit is to:
precharge bit lines associated with the second set of memory cells while data from the first set of memory cells is being read; and
write data to the second set of memory cells after the precharge of the bit lines associated with the second set of memory cells.

17. One or more non-transitory, computer-readable media having instructions, stored thereon, that when executed cause a memory controller to:
precharge bit lines associated with respective memory cells of a set of memory cells that are multiplexed with a sense amplifier;
provide a single assertion of a word line signal to the set of memory cells; and
consecutively read data from the set of memory cells based on the precharge and the single assertion of the word line signal.

18. The one or more media of claim 17 , wherein, to consecutively read the data from the set of memory cells, the instructions are to cause the memory controller to:
assert a first read column select signal associated with a first memory cell of the set of memory cells;
enable, responsive to de-assertion of the first read column select signal, the sense amplifier to read a first data bit stored by the first memory cell; and
precharge, responsive to disablement of the sense amplifier, the sense amplifier to prepare the sense amplifier to read a second data bit stored by a second memory cell of the set of memory cells.

19. The one or more media of claim 18 , wherein a combined duration of the assertion of the first read column select signal, the enablement of the sense amplifier, and the precharge of the sense amplifier is one phase of a clock signal associated with the memory controller.

20. The one or more media of claim 18 , wherein the set of memory cells is a first set of memory cells, and wherein the instructions, when executed, are further to cause the memory controller to:
precharge bit lines associated with a second set of m

Assignees

• Intel Corp

Inventors

• Khellah Muhammad M
• Paul Somnath
• Augustine Charles
• Majumder Turbo
• Bang Suyoung

Classifications

• G11C7/103

  using serially addressed read-write data registers (G11C7/1036 takes precedence) · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C7/1012

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title

• G11C11/418

  Address circuits · CPC title

• G11C7/1051

  Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits · CPC title