Vertical alignment liquid crystal display

Patent metadata

Field	Value
Publication number	US-10755653-B2
Application number	US-201816112502-A
Country	US
Kind code	B2
Filing date	Aug 24, 2018
Priority date	Apr 2, 2018
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

Provided is a vertical alignment liquid crystal display, comprising a plurality of data lines, a plurality of scan lines and a plurality of common electrode lines; the scan lines intersect the data lines and the common electrode lines to form a plurality of pixel regions arranged in an array; the sub pixel region comprises a first thin film transistor, a second thin film transistor and a sub pixel, and gates of the first thin film transistor and second thin film transistor are coupled to a same scan line, and drains of the first thin film transistor and second thin film transistor are respectively coupled to a data line and a common electrode line which are adjacent, and sources of the first thin film transistor and second thin film transistor are coupled to the sub pixel; the main pixel region comprises a third thin film transistor and a sub pixel.

First claim

What is claimed is:

1. A vertical alignment liquid crystal display, comprising a plurality of data lines, a plurality of scan lines and a plurality of common electrode lines;
wherein the plurality of scan lines are disposed to intersect the plurality of data lines and the plurality of common electrode lines to form a plurality of pixel regions arranged in an array; the plurality of data lines and the plurality of common electrode lines are spaced apart from each other;
each of the plurality of pixel regions comprise a sub pixel region and a main pixel region, and the plurality of sub pixel regions and the plurality of main pixel regions of the plurality of pixel regions arranged in an array are spaced apart from each other;
the sub pixel region comprises a first thin film transistor, a second thin film transistor and a sub pixel, and a gate of the first thin film transistor and a gate of the second thin film transistor are coupled to a same scan line of the plurality of scan lines, and a drain of the first thin film transistor and a drain of the second thin film transistor are respectively coupled to a data line and a common electrode line which are adjacent, and a source of the first thin film transistor and a source of the second thin film transistor are both coupled to the sub pixel of the sub pixel region;
the main pixel region comprises a third thin film transistor and a sub pixel, and a gate of the third thin film transistor is coupled to a scan line of the plurality of scan lines, and a drain of the third thin film transistor is coupled to the data line or the common electrode line, and a source of the third thin film transistor is coupled to the sub pixel of the main pixel region;
wherein as the liquid crystal display is in operation, two adjacent data lines are used to access data signals of opposite waveforms to prevent occurrence of signal crosstalk between the two adjacent data lines;
wherein the plurality of pixel regions are divided into a plurality of rows of sub pixel regions and a plurality of rows of main pixel regions, and the plurality of rows of sub pixel regions and the plurality of rows of main pixel regions are arranged spaced apart from each other;
wherein the sub pixels in two adjacent sub pixel regions in each row of sub pixel regions are respectively connected to the scan lines on both sides of the row of sub pixel regions with the first thin film transistor and the second thin film transistor;
the sub pixels in adjacent two main pixel regions in each row of main pixel regions are respectively connected to the scan lines on both sides of the row of main pixel regions with the third thin film transistor.

2. The vertical alignment liquid crystal display according to claim 1 , wherein each row of pixel regions in the plurality of pixel regions comprises a plurality of sub pixel regions and a plurality of main pixel regions that are spaced apart from each other.

3. The vertical alignment liquid crystal display according to claim 2 , wherein the sub pixel region and the sub pixel in the main pixel region, which are adjacent, in each row of pixel regions are respectively connected to the scan lines on both sides of the row of pixel regions.

4. The vertical alignment liquid crystal display according to claim 1 , wherein the first thin film transistor, the second thin film transistor and the third thin film transistor in each row of pixel regions are commonly driven by the scan lines on both sides of the row of pixel regions, and each scan line is used to drive the first thin film transistor, the second thin film transistor and the third thin film transistor of one row of pixel regions.

5. The vertical alignment liquid crystal display according to claim 1 , wherein two adjacent third thin film transistors in each row of main pixel regions are respectively connected to adjacent data line and common electrode line.

6. The vertical alignment liquid crystal display according to claim 1 , wherein the sub pixel comprises a liquid crystal capacitor.

7. A vertical alignment liquid crystal display, comprising a plurality of data lines, a plurality of scan lines and a plurality of common electrode lines;
wherein the plurality of scan lines are disposed to intersect the plurality of data lines and the plurality of common electrode lines to form a plurality of pixel regions arranged in an array; the plurality of data lines and the plurality of common electrode lines are spaced apart from each other;
each of the plurality of pixel regions comprise a sub pixel region and a main pixel region, and the plurality of sub pixel regions and the plurality of main pixel regions of the plurality of pixel regions arranged in an array are spaced apart from each other;
the sub pixel region comprises a first thin film transistor, a second thin film transistor and a sub pixel, and the sub pixel comprises a liquid crystal capacitor, and a gate of the first thin film transistor and a gate of the second thin film transistor are coupled to a same scan line of the plurality of scan lines, and a drain of the first thin film transistor and a drain of the second thin film transistor are respectively coupled to a data line and a common electrode line which are adjacent, and a source of the first thin film transistor and a source of the second thin film transistor are both coupled to the sub pixel of the sub pixel region;
the main pixel region comprises a third thin film transistor and a sub pixel, and a gate of the third thin film transistor is coupled to a scan line of the plurality of scan lines, and a drain of the third thin film transistor is coupled to the data line or the common electrode line, and a source of the third thin film transistor is coupled to the sub pixel of the main pixel region;
wherein the first thin film transistor, the second thin film transistor and the third thin film transistor in each row of pixel regions are commonly driven by two scan lines on both sides of the row of pixel regions, and each of the scan lines on both sides of the row of pixel regions is used to drive the first thin film transistor, the second thin film transistor and the third thin film transistor of one row of pixel regions;
wherein as the liquid crystal display is in operation, two adjacent data lines are used to access data signals of opposite waveforms to prevent occurrence of signal crosstalk between the two adjacent data lines;
wherein the plurality of pixel regions are divided into a plurality of rows of sub pixel regions and a plurality of rows of main pixel regions, and the plurality of rows of sub pixel regions and the plurality of rows of main pixel regions are arranged spaced apart from each other;
wherein the sub pixels in two adjacent sub pixel regions in each row of sub pixel regions are respectively connected to the scan lines on both sides of the row of sub pixel regions with the first thin film transistor and the second thin film transistor;
the sub pixels in adjacent two main pixel regions in each row of main pixel regions are respectively connected to the scan lines on both sides of the row of main pixel regions with the third thin film transistor.

8. The vertical alignment liquid crystal display according to claim 7 , wherein each row of pixel regions in the plurality of pixel regions comprises a plurality of sub pixel regions and a plurality of main pixel regions that are spaced apart from each other.

9. The vertical alignment liquid crystal display according to claim 8 , wherein the sub pixel region and the sub pixel in the main pixel region, which are adjacent, in each row of pixel regions are respectively connected to the scan lines on both sides of the row of pixel regions.

10. The vertical alignment liquid crys

Assignees

• Shenzhen China Star Optoelectronics Semiconductor Display Tech Co Ltd

Inventors

• Hao Sikun

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• G02F1/134345

  Subdivided pixels, e.g. for grey scale or redundancy · CPC title

• G02F1/136245

  having complementary transistors · CPC title

• G09G2320/066

  for control of contrast · CPC title