Method of fabricating an electrical filter for use with superconducting-based computing systems

US10755190B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10755190-B2
Application numberUS-201615382278-A
CountryUS
Kind codeB2
Filing dateDec 16, 2016
Priority dateDec 21, 2015
Publication dateAug 25, 2020
Grant dateAug 25, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An electrical filter includes a dielectric substrate with inner and outer coils about a first region and inner and outer coils about a second region, a portion of cladding removed from wires that form the coils and coupled to electrically conductive traces on the dielectric substrate via a solder joint in a switching region. An apparatus to thermally couple a superconductive device to a metal carrier with a through-hole includes a first clamp and a vacuum pump. A composite magnetic shield for use at superconductive temperatures includes an inner layer with magnetic permeability of at least 50,000; and an outer layer with magnetic saturation field greater than 1.2 T, separated from the inner layer by an intermediate layer of dielectric. An apparatus to dissipate heat from a superconducting processor includes a metal carrier with a recess, a post that extends upwards from a base of the recess and a layer of adhesive on top of the post. Various cryogenic refrigeration systems are described.

First claim

Opening claim text (preview).

We claim: 1. A method of fabricating an electrical filter for use with differential signals, the method comprising: winding a first length of wire about a first region of a dielectric substrate, to form a first inner coil of wire, wherein the first length of wire comprises a first wire core and a first resistive cladding; winding the first length of wire about a second region of the dielectric substrate, to form a second inner coil of wire, wherein the first and the second regions of the dielectric substrate are separated by a switching region of the dielectric substrate; winding a second length of wire around the first inner coil of wire, to form a first outer coil of wire, wherein the second length of wire comprises a second wire core and a second resistive cladding; winding the second length of wire around the second inner coil of wire, to form a second outer coil of wire; exposing a portion of the first and the second wire core in the switching region by removing a first portion of the first and the second resistive cladding, respectively, and tapering a second portion of the first and the second resistive cladding on each side of the first portion of the first and the second wire cladding, respectively; soldering the first and the second lengths of wire to each of a first and a second conductive trace in the switching region to form a solder joint, wherein the solder joint overlies the exposed portion of the first and the second wire core, and overlies the tapered portion of the first and the second cladding, and wherein the solder joint electrically couples the first and the second wire cores to the first and the second conductive traces, and mechanically couples the first and the second lengths of wire to the switching region; and cutting each of the first and the second lengths of wire between the first and the second conductive trace, to form a first conductive signal path comprising the first inner coil of wire and the second outer coil of wire, and a second conductive signal path comprising the first outer coil of wire and the second inner coil of wire. 2. The method of claim 1 wherein winding the first length of wire about the first region of the dielectric substrate includes winding a first length of continuous superconductive wire about the first region of the dielectric substrate, the first length of continuous superconductive wire comprising a core material that is superconducting below a first critical temperature, and wherein winding the second length of wire about the first region of the dielectric substrate includes winding a second length of continuous superconductive wire about the first region of the dielectric substrate, the second length of continuous superconductive wire comprising a core material that is superconducting below a second critical temperature. 3. The method of claim 1 wherein exposing the portion of the first and the second wire core in the switching region by removing the first portion of the first and the second resistive cladding, respectively, and tapering the second portion of the first and the second resistive cladding on each side of the first portion of the first and the second wire resistive cladding, respectively, includes applying an etchant to the portion of the first and the second lengths of wire. 4. The method of claim 3 , further comprising: heating the switching region to cause the etchant to corrode the first and the second resistive claddings. 5. The method of claim 3 , further comprising: applying a protective mask to the first and the second conductive traces to protect the first and the second conductive traces from the etchant, wherein soldering the first and the second lengths of wire to each of the first and the second conductive trace in the switching region to form the solder joint includes removing the protective mask from the first and the second conductive traces. 6. The method of claim 3 wherein applying the etchant to the portion of the first and the second lengths of wire includes applying ferric chloride to the portion of the first and the second lengths of wire. 7. The method of claim 1 wherein winding the first length of wire about the first or the second region of the dielectric substrate, to form the first or the second inner coil of wire, respectively, includes winding a first number of turns in the first length of wire, and winding the second length of wire about the first or the second region of the dielectric substrate, to form the first or the second outer coil of wire, respectively, includes winding a second number of turns in the second length of wire, wherein the second number of turns is less than or equal to the first number of turns. 8. The method of claim 1 wherein winding the first length of wire about the first region of the dielectric substrate, to form the first inner coil of wire includes winding the first length of wire in a first direction about the dielectric substrate, and winding the second length of wire about the first region of the dielectric substrate, to form the first outer coil of wire includes winding the second length of wire in a second direction about the dielectric substrate, wherein the first direction is the same as the second direction. 9. The method of claim 1 wherein winding the first and the second length of wire includes winding the first and the second length of wire each with respective niobium-titanium wire cores, and copper-nickel claddings.

Assignees

Inventors

Classifications

  • H01F41/048Primary

    Superconductive coils · CPC title

  • Balance-balance networks · CPC title

  • Forming taps or terminals while winding, e.g. by wrapping or soldering the wire onto pins, or by directly forming terminals from the wire · CPC title

  • Metal wires as connectors or conductors · CPC title

  • Lay-out of balanced signal pairs, e.g. differential lines or twisted lines · CPC title

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What does patent US10755190B2 cover?
An electrical filter includes a dielectric substrate with inner and outer coils about a first region and inner and outer coils about a second region, a portion of cladding removed from wires that form the coils and coupled to electrically conductive traces on the dielectric substrate via a solder joint in a switching region. An apparatus to thermally couple a superconductive device to a metal c…
Who is the assignee on this patent?
D Wave Systems Inc
What technology area does this patent fall under?
Primary CPC classification H01F41/048. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 25 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).