Fast cache invalidation response using cache class attributes

Patent metadata

Field	Value
Publication number	US-10754775-B2
Application number	US-201816222696-A
Country	US
Kind code	B2
Filing date	Dec 17, 2018
Priority date	Nov 30, 2018
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

A memory management unit responds to an invalidate by class command by identifying a marker for a class of cache entries that the invalidate by class command is meant to invalidate. The memory management unit stores the active marker as a retired marker and then sets the active marker to the next available marker. Thereafter, the memory management sends an acknowledgement signal (e.g., to the operating system) while invalidating the cache entries having the class and the retired marker in the background. By correlating markers with classes of cache entries, the memory management can more quickly respond to class invalidation requests.

First claim

What is claimed is:

1. A memory management unit comprising:
an asynchronous command interface;
cache memory invalidation logic adapted to:
identify an active marker for a class of cache entries;
set the active marker as a retired marker; and
on condition that a next marker is available to be used, operate the asynchronous command interface to immediately respond to an invalidate by class command for the class with an acknowledgement signal, and perform a background invalidation of the cache entries having the class and the retired marker.

2. The memory management unit of claim 1 , the cache memory invalidation logic further adapted to:
determine the next marker by incrementing the active marker for the class of cache entries by an increment value;
on condition that the next marker is not available to be used, wait for the next marker to be available to be used before invalidating the cache entries having the class and the retired marker.

3. The memory management unit of claim 2 , wherein the cache memory invalidation logic is further adapted to wait until the next marker is available to be used before operating the asynchronous command interface to send the acknowledgement signal.

4. The memory management unit of claim 2 , wherein the increment value is one.

5. The memory management unit of claim 1 , wherein the class corresponding to the invalidate by class command corresponds to page table entries in at least one translation look-aside buffer.

6. The memory management unit of claim 1 , further comprising prioritization logic to prioritize address translations for active contexts over execution of the invalidate by class command.

7. The memory management unit of claim 1 , the cache memory invalidation logic further adapted to:
invalidate cache entries allocated for in-flight cache fill requests for cache entries having the retired marker; and
discard responses received for the in-flight cache fill requests.

8. A memory management unit comprising:
an asynchronous command interface to receive and an invalidate by class command from an operating system and operable to respond to the invalidate by class command with an asynchronous acknowledgement signal;
cache memory invalidation logic coupled to the asynchronous command interface and responsive to the invalidate by class command, the cache memory invalidation logic adapted to:
identify an active marker for a class of cache entries identified with the invalidate by class command;
set the active marker as a retired marker;
determine a next marker by incrementing the active marker for the class by an increment value;
on condition that the next marker is available to be used:
set the active marker to the next marker;
operate the asynchronous command interface to send the acknowledgement signal; and
invalidate the cache entries having the class and the retired marker.

9. The memory management unit of claim 8 , the cache memory invalidation logic further adapted to:
on condition that the next marker is not available to be used:
wait for the next marker to be available to be used before invalidating the cache entries having the class and the retired marker; and
wait until the next marker is available to be used before causing the asynchronous command interface to send the acknowledgement signal.

10. The memory management unit of claim 8 , wherein the increment value is one.

11. The memory management unit of claim 8 , wherein the class corresponding to the invalidate by class command corresponds to page table entries in at least one translation look-aside buffer.

12. The memory management unit of claim 8 , further comprising prioritization logic to prioritize address translations for active contexts over execution of the invalidate by class command.

13. The memory management unit of claim 8 , the cache memory invalidation logic further adapted to:
invalidate cache entries allocated for in-flight cache fill requests for cache entries having the retired marker; and
discard responses received for the in-flight cache fill requests.

14. The memory management unit of claim 8 , wherein the cache memory invalidation logic is implemented using a state machine.

15. The memory management unit of claim 8 , wherein the active marker comprises N-bits, where N is derived from runtime profiling of use of the invalidate by class command by the operating system.

16. A memory management unit comprising:
a plurality of cache entries; and
cache memory invalidation logic to assign an active marker to a class of the cache entries and operate an asynchronous command interface to immediately acknowledge an invalidate by class command for the class and the marker while performing a background invalidation of the cache entries having the class and a retired marker.

17. The memory management unit of claim 16 , the cache memory invalidation logic to determine a next marker by incrementing a previous active marker for the class of cache entries by an increment value and to wait for the next marker to be available to be used before invalidating the cache entries having the class and the retired marker.

18. The memory management unit of claim 17 , the cache memory invalidation logic to wait until the next marker is available to be used before acknowledging the invalidate by class command.

19. The memory management unit of claim 17 , wherein the increment value is set to one.

20. The memory management unit of claim 16 , wherein the class corresponding to the invalidate by class command corresponds to page table entries in at least one translation look-aside buffer.

Assignees

• Nvidia Corp
• Nvidia Corp

Inventors

• Gupta Jay
• Padmanabhan Gosagan
• Mittal Devesh
• Agarwal Kaushal

Classifications

• G06F12/0808 Primary

  with cache invalidating means (G06F12/0815 takes precedence) · CPC title

• G06F2212/683

  Invalidation · CPC title

• G06F12/1036 Primary

  for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) · CPC title

• G06F2212/1044

  Space efficiency improvement · CPC title

• G06F12/1045

  associated with a data cache · CPC title