Random number generator

Patent metadata

Field	Value
Publication number	US-10754618-B2
Application number	US-201816035798-A
Country	US
Kind code	B2
Filing date	Jul 16, 2018
Priority date	Jul 27, 2017
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

A random number generation device includes conductive lines including interruptions and a number of conductive vias. A via is located at each interruption. Each via randomly fills or does not fill the interruption. A circuit is capable of determining the electric continuity or lack of continuity of the conductive lines.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a plurality of conductive paths, wherein each of the plurality of conductive paths comprises, within a metal level, a plurality of discrete metal lines and a plurality of interruptions, adjacent ones of the plurality of discrete metal lines in the metal level being separated by one of the plurality of interruptions;
a plurality of conductive vias, each of the plurality of conductive vias being located at an associated one of the plurality of interruptions, wherein the plurality of conductive vias comprises a first type of vias and a second type of vias, wherein the first type of vias fill the associated one of the plurality of interruptions, and the second type of vias do not fill the associated one of the plurality of interruptions; and
wherein an identification number of the semiconductor device is determinable from the plurality of conductive paths, and wherein each of the plurality of conductive paths correspond to a digit value of the identification number based on a number of the first type of vias and the second type of vias in the corresponding conductive path.

2. The device of claim 1 , wherein the conductive paths of the plurality of conductive paths are metallizations of a level of an interconnection network.

3. The device of claim 2 , wherein each conductive via of the first type of vias of a conductive path of the plurality of conductive paths connects the conductive path with a lower level of the interconnection network.

4. The device of claim 3 , wherein each conductive via of the second type of vias of the conductive path of the plurality of conductive paths does not connect the conductive path with of the interconnection network.

5. The device of claim 1 , wherein between 40% and 60% of the plurality of conductive vias comprise the first type of vias.

6. The device of claim 1 , wherein the identification number comprises at least 128 values.

7. The device of claim 1 , wherein the associated one of the plurality of interruptions of at least one conductive via of the plurality of conductive vias separates three adjacent discrete metal lines.

8. The device of claim 1 , wherein a multi-level conductive path of the plurality of conductive paths is partially on a level of an interconnection network and partially on another level of the interconnection network.

9. The device of claim 1 , wherein at least one of the second type of vias is misaligned with at least one of the adjacent discrete metal lines separated by the at least one of the second type of vias.

10. The device of claim 1 , wherein one conductive via of the plurality of conductive vias is located at each interruption.

11. The device of claim 1 , further comprising a sense circuit configured to measure an electrical continuity or lack of electrical continuity to determine the digit value for each of the plurality of conductive paths.

12. The device of claim 11 , wherein the sense circuit determines the electrical continuity or lack of electrical continuity by measuring the resistance on each of the plurality of conductive paths.

13. The device of claim 1 , wherein between 40% and 60% of the plurality of conductive paths contains at least one conductive via of the second type of vias.

14. A method of manufacturing a random number generation device, the method comprising:
forming a first mask on an insulator layer, the first mask comprising a plurality of first openings for defining a plurality of conductive paths wherein each of the plurality of conductive paths comprises, within a metal level, a plurality of discrete metal lines and a plurality of interruptions, adjacent ones of the plurality of discrete metal lines in the metal level being separated by one of the plurality of interruptions;
forming a second mask on the first mask, the second mask comprising a plurality of second openings for defining a plurality of vias, the second mask being placed in such a way that each of the plurality of vias is located at an associated one of the plurality of interruptions; and
applying a conductor within the plurality of vias using a manufacturing technology, lateral dimensions of the plurality of second openings being selected according to the manufacturing technology so inaccuracies randomly occurring during the manufacturing produce a first type of vias that fill the associated one of the plurality of interruptions, and a second type of vias that do not fill the associated one of the plurality of interruptions.

15. The method of claim 14 , wherein the insulator layer is part of an interconnection network.

16. The method of claim 15 , comprising the steps of:
etching a plurality of first cavities through the plurality of second openings of the second mask without reaching a lower level of the interconnection network;
removing the second mask;
etching a plurality of second cavities through the plurality of first openings, each second cavity extending through a bottom of an associated one of the plurality of first cavities to reach the lower level of the interconnection network;
removing the first mask; and
wherein applying the conductor comprises filling the plurality of first cavities and the plurality of second cavities with conductive material.

17. The method of claim 14 , wherein, at least one of the second openings partially overlaps at least one of the first openings so a conductor applied within a via defined by the at least one of the second openings has two distinct thicknesses within the via.

18. A device comprising:
a plurality of lower conductive lines;
an interlevel dielectric layer overlying the lower conductive lines;
a plurality of upper conductive lines overlying the interlevel dielectric layer, each upper conductive line extending over more than one of the lower conductive lines;
a plurality of vias, each via located at an intersection between an associated one of the plurality of lower conductive lines and an associated one of the plurality of upper conductive lines, a resistance between the associated one of the plurality of lower conductive lines and the associated one of the plurality of upper conductive lines being either higher than a threshold or lower than the threshold due to an alignment of the via; and
a sense circuit configured to determine whether the resistance between the associated one of the plurality of lower conductive lines of a via and the associated one of the plurality of upper conductive lines of the via is higher than the threshold or lower than the threshold.

19. The device of claim 18 , wherein the lower conductive lines of the plurality of lower conductive lines and the upper conductive lines of the plurality of upper conductive lines are metallizations of a level of an interconnection network of an integrated circuit, the sense circuit being part of the integrated circuit.

20. The device of claim 18 , wherein the plurality of vias comprises a first type of vias that connects the associated one of the plurality of lower conductive lines with the associated one of the plurality of lower conductive lines of and a second type of vias that does not connect the associated one of the plurality of lower conductive lines with the associated one of the plurality of upper conductive lines.

21. The device of claim 18 , wherein the resistance between the associated one of the plurality of lower conductive lines and the associated one of the plurality of upper conductive lines is higher than the threshold for between 40% and 60% of the

Assignees

• Stmicroelectronics Rousset
• St Microelectronics Crolles 2 Sas

Inventors

• Froment Benoit
• Petitdidier Sebastien
• Lisart Mathieu
• Voisin Jean-Marc

Classifications

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H04L9/0866 Primary

  involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics · CPC title

• G06F7/588 Primary

  Random number generators, i.e. based on natural stochastic processes · CPC title

• G06F21/70

  Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer · CPC title

• H01L21/76829

  Electricity · mapped topic