Fabrication process of polymer based photonic apparatus and the apparatus

Patent metadata

Field	Value
Publication number	US-10754093-B2
Application number	US-201916411583-A
Country	US
Kind code	B2
Filing date	May 14, 2019
Priority date	May 15, 2018
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

A method of fabricating polymer modulators includes forming an insulating layer on a platform and depositing and patterning a ground electrode on the insulating layer. A bottom polymer cladding layer, a first blocking layer, a polymer core layer, a second blocking layer, and a top polymer cladding layer are deposited in order. A third blocking layer is deposited on the top cladding layer and patterned to define vias which are used to etch ground openings through the top polymer cladding layer, the second blocking layer, the core layer, the first blocking layer, and the bottom cladding layer to the ground electrode. The openings are filled with electrically conductive material from electrical communication with the ground electrode to a surface of the top polymer cladding layer. The third blocking layer is removed and electrical contacts are formed on the top polymer cladding layer in electrical communication with the electrically conductive material.

First claim

Having fully described the invention in such clear and concise terms as to enable those skilled in the art to understand and practice the same, the invention claimed is:

1. A method of fabricating polymer based photonic apparatus comprising the steps of:
providing a platform;
forming a layer of dielectric or insulating material on the platform;
depositing and patterning a ground electrode on the layer of dielectric or insulating material;
depositing a bottom cladding layer of polymer material on the ground electrode and on exposed portions of the layer of dielectric or insulating material;
depositing a first blocking layer on the bottom cladding layer;
depositing a core layer of polymer material on the first blocking layer;
depositing a second blocking layer on the core layer;
depositing a top cladding layer of polymer material on the second blocking layer;
depositing a third blocking layer on the top cladding layer and patterning the third blocking layer to define vias;
using the vias, etching ground openings through the top polymer cladding layer, the second blocking layer, the core layer, the first blocking layer, and the bottom cladding layer to the ground electrode;
depositing an electrically conductive material in the ground openings, the electrically conductive material extending from electrical communication with the ground electrode to a surface of the top polymer cladding layer; and
removing the third blocking layer and depositing electrical contacts on the top polymer cladding layer, at least some of the electrical contacts being in electrical communication with the electrically conductive material.

2. The method as claimed in claim 1 wherein the step of providing the platform includes providing a wafer of Si, SiGe, InP, GaAs, GaN, or GaSb.

3. The method as claimed in claim 2 wherein the step of providing the platform includes providing a silicon wafer and the step of forming the layer of dielectric or insulating material includes oxidizing the silicon wafer to produce a layer of silicon oxide.

4. The method as claimed in claim 1 wherein the step of depositing and patterning the ground electrode includes depositing multiple layers of metallization.

5. The method as claimed in claim 4 wherein the step of depositing and patterning the ground electrode includes depositing multiple layers of titanium and gold.

6. The method as claimed in claim 1 wherein the steps of depositing the bottom cladding layer of polymer material, depositing the core layer of polymer material, and depositing the top cladding layer of polymer material, each include spin coating a layer of formulated solution containing a selected polymer and baking the layer.

7. The method as claimed in claim 6 wherein the step of depositing the core layer of polymer material includes depositing a layer of polymer 1.6 μm (micrometers)+/−0.2 μm thick.

8. The method as claimed in claim 6 wherein the step of depositing the bottom cladding layer of polymer material includes depositing a layer of polymer material 3.5 μm (micrometers)+/−0.5 μm thick.

9. The method as claimed in claim 6 wherein the step of depositing the top cladding layer of polymer material includes depositing a layer of polymer material 3.5 μm (micrometers)+/−0.5 μm thick.

10. The method as claimed in claim 1 wherein the steps of depositing the first blocking layer and depositing the second blocking layer each include depositing a layer including aluminum oxide.

11. The method as claimed in claim 10 wherein the steps of depositing the first and second blocking layers of aluminum oxide includes depositing the aluminum oxide by sputtering.

12. The method as claimed in claim 10 wherein the steps of depositing the first and second blocking layers each include depositing a layer of aluminum oxide approximately 50 nm thick+/−10 nm.

13. The method as claimed in claim 1 wherein the step of depositing and patterning the ground electrode includes patterning the ground electrode to produce multiple spaced apart ground electrode contacts.

14. The method as claimed in claim 1 further including a step of patterning and etching the core layer to form ridges defining multiple waveguide ridges, each ridge of the multiple ridges overlying a ground electrode contact of the multiple ground electrode contacts.

15. The method as claimed in claim 4 wherein the step of patterning and etching the core layer to form ridges includes forming the ridges 0.8 μm+/−0.1 μm high.

16. The method as claimed in claim 1 wherein the step of depositing electrical contacts on the top polymer cladding layer includes depositing a gold seed layer on the top polymer cladding layer, forming a photoresist pattern on the gold seed layer defining openings overlying the electrically conductive material in the ground openings and each ridge of the multiple ridges, electroplating gold contacts in the openings, removing the photoresist pattern and removing the gold seed layer between the gold contacts.

17. A method of fabricating polymer based photonic apparatus comprising the steps of:
providing a semiconductor wafer;
forming a layer of dielectric or insulating material on the semiconductor wafer;
depositing and patterning a ground electrode on the layer of dielectric or insulating material;
depositing a bottom cladding layer of polymer material on the ground electrode and on exposed portions of the layer of dielectric or insulating material including spin coating a layer of formulated solution containing a selected polymer and baking the layer;
depositing a first blocking layer on the bottom cladding layer;
depositing a core layer of polymer material on the first blocking layer including spin coating a layer of formulated solution containing a selected polymer and baking the layer;
depositing a second blocking layer on the core layer;
depositing a top cladding layer of polymer material on the second blocking layer including spin coating a layer of formulated solution containing a selected polymer and baking the layer;
depositing a third blocking layer on the top cladding layer and patterning the third blocking layer to define vias;
using the vias, etching ground openings through the top polymer cladding layer, the second blocking layer, the core layer, the first blocking layer, and the bottom cladding layer to the ground electrode;
depositing an electrically conductive material in the ground openings, the electrically conductive material extending from electrical communication with the ground electrode to a surface of the top polymer cladding layer; and
removing the third blocking layer and depositing electrical contacts on the top polymer cladding layer, at least some of the electrical contacts being in electrical communication with the electrically conductive material.

18. The method as claimed in claim 17 wherein the steps of depositing the first blocking layer and depositing the second blocking layer each include depositing a layer including aluminum oxide.

19. The method as claimed in claim 17 wherein the step of depositing and patterning the ground electrode includes patterning the ground electrode to produce multiple spaced apart ground electrode contacts.

20. The method as claimed in claim 17 further including a step of patterning and etching the core layer to form ridges defining multiple waveguide ridges, each ridge of the multiple ridges overlying a ground electrode contact of the multiple ground electrode contacts.

21. The method as claimed in claim 17 wherein the st

Assignees

• Lightwave Logic Inc

Inventors

• Liu Zhiming
• Lebby Michael
• Shaw Brian
• Becker Richard
• Yi Youngwoo

Classifications

• G02B2006/12176

  Etching · CPC title

• G02B6/1221 Primary

  made from organic materials · CPC title

• G02B2006/12173

  Masking · CPC title

• G02F1/065 Primary

  in an optical waveguide structure · CPC title

• G02B2006/1219

  Polymerisation · CPC title