Apparatus and method for a vapor cell atomic frequency reference

Patent metadata

Field	Value
Publication number	US-10749539-B2
Application number	US-201816031458-A
Country	US
Kind code	B2
Filing date	Jul 10, 2018
Priority date	Mar 26, 2018
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

A chip scale atomic clock (CSAC) includes a temperature stabilized physics system and a temperature stabilized electronics circuitry electrically coupled to the temperature stabilized physics system. Atomic clocks utilize an optical signal having a frequency component. The temperature stabilization increases frequency stability. The temperature stabilized physics system includes a vapor cell and a magnetic field coil, and is enclosed in a magnetic shield. When an ambient temperature of a chip scale atomic clock increases, fluid is extended away, due to thermal expansion, from at least one reservoir towards or away from a thermally isolated subsystem in at least one of the temperature stabilized electronics circuitry and the temperature stabilized physics system.

First claim

What is claimed is:

1. A chip scale atomic clock (CSAC), comprising:
a temperature stabilized physics system, comprising a vapor cell and a magnetic field coil, and which is enclosed in a magnetic shield; and

temperature stabilized electronics circuitry electrically coupled to the temperature stabilized physics system, where the temperature stabilized electronics circuitry is configured to at least one of i) control physics system components and ii) process data sent to and/or received by the physics system components; and
wherein when an ambient temperature of the CSAC increases, extending fluid away, due to thermal expansion, from at least one reservoir towards or away from a thermally isolated subsystem in at least one of the temperature stabilized electronics circuitry and the temperature stabilized physics system, where each of the temperature stabilized electronics circuitry and the temperature stabilized physics system comprises a non-thermally isolated subsystem and a thermally isolated subsystem that are thermally isolated from one another.

2. The CSAC of claim 1 , further comprising a non-temperature stabilized electronics circuitry electrically coupled to at least one of the temperature stabilized physics system and the temperature stabilized electronics circuitry.

3. The CSAC of claim 2 , wherein the non-temperature stabilized electronics circuitry comprises at least one of controller circuitry and power conditioning circuitry.

4. The CSAC of claim 3 , wherein the non-temperature stabilized electronics circuitry further includes at least one of: a crystal oscillator, a phase locked loop, at least one heater current control circuit, and at least one coil current control circuit.

5. The CSAC of claim 1 , wherein a substantially constant set point temperature of the thermally isolated subsystem is maintained, in the at least one of the temperature stabilized electronics circuitry and the temperature stabilized physics system, by increasing thermal energy dissipated from the thermally isolated subsystem to the non-thermally isolated subsystem through the fluid, where the substantially constant set point temperature means a temperature within a range of temperatures that does not decrease the stability of the CSAC.

6. The CSAC of claim 1 , wherein a second magnetic shield encloses only the temperature stabilized electronics circuitry.

7. The CSAC of claim 1 wherein a third magnetic shield encloses the temperature stabilized physics system and the temperature stabilized electronics circuitry.

8. The CSAC of claim 1 , wherein at least one of the temperature stabilized electronics circuitry and the temperature stabilized physics system further comprises a passive heat sink.

9. The CSAC of claim 8 , wherein the at least one of the temperature stabilized electronics circuitry and the temperature stabilized physics system comprises:
a first substrate;
a second substrate;
components attached to the second substrate;
at least one tether coupling the first substrate and the second substrate;
wherein the at least one passive heat sink comprises:
at least one capillary in or on at least one of the at least one tether; and
at least reservoir coupled to each of the at least one capillary;

wherein the at least one reservoir is configured to store liquid;
wherein the at least one reservoir is mounted in or on at least one of the first substrate and the second substrate; and
wherein the liquid is configured to flow through each of the at least one capillary as the ambient temperature of the CSAC fluctuates.

10. The CSAC of claim 9 , wherein the first substrate and the second substrate comprises silicon; and
wherein the at least one capillary comprises a recess in a dielectric.

11. The CSAC of claim 9 , wherein electrical conductors formed on the tether electrically couple the first substrate to the second substrate.

12. The CSAC of claim 1 , wherein the temperature stabilized electronics circuitry comprises:
a first substrate;
a second substrate;
at least one electrical component mounted on the second substrate;
at least one tether coupled between the first substrate and the second substrate, and configured to thermally isolate the first substrate from the second substrate;
a body, wherein the first substrate is attached to the body; and
a lid attached to the body, wherein the first substrate, the second substrate, the at least one electrical component, and the at least one tether are enclosed in by the lid and body.

13. The CSAC of claim 12 , wherein the lid is hermetically sealed to the body; and
wherein the first substrate, the second substrate, the at least one electrical component, and the at least one tether are enclosed in a vacuum by the lid and body.

14. The CSAC of claim 12 , where the tether comprises at least one conductor that conductively couples the first substrate and the second substrate.

15. A method, comprising:
when the ambient temperature of a chip scale atomic clock (C SAC) increases, extending fluid away, due to thermal expansion, from at least one reservoir towards or away from a thermally isolated subsystem in at least one of the temperature stabilized electronics circuitry and the temperature stabilized physics system, where the CSAC comprises a temperature stabilized electronics circuitry and a temperature stabilized physics system, each of which comprises a non-thermally isolated subsystem and a thermally isolated subsystem that are thermally isolated from one another; and
maintaining a substantially constant set point temperature of the thermally isolated subsystem, in the at least one of the temperature stabilized electronics circuitry and the temperature stabilized physics system, by increasing thermal energy dissipated from the thermally isolated subsystem to the non-thermally isolated subsystem through the fluid, where the substantially constant set point temperature means a temperature with in a range of temperatures that does not decrease the stability of the CSAC.

16. The method of claim 15 , wherein extending fluid away from the at least one reservoir comprises fluid flowing through at least one capillary in at least one tether, where the at least one capillary is coupled to the at least one reservoir.

17. The method of claim 15 , further comprising:
increasing an ambient temperature of the CSAC;
retracting fluid, due to thermal contraction, towards the at least one reservoir away from or towards the thermally isolated subsystem; and
maintaining the substantially constant set point temperature of the thermally isolated subsystem by decreasing the thermal energy dissipated from the thermally isolated subsystem to the non-thermally isolated subsystem through the fluid.

18. A method of forming a passive heat sink in a temperature stabilized electronics circuitry or a temperature stabilized physics system of a chip scale atomic clock (CSAC), comprising:
forming a first substrate with a first layer on the first substrate and second substrate with the first layer on the second substrate from a single substrate with the first layer on the single substrate;
forming at least one opening in the first layer over at least one of the first substrate and the second substrate;
forming a reservoir under each opening;
filling each reservoir with a fluid;
forming at least one recess in a second layer on a handle wafer;
attaching the second layer to the first layer; and
removing the handle wafer.

19. The method of claim 18 , wherein the filling each reservoir with the fluid c

Assignees

• Honeywell Int Inc

Inventors

• Kriz Jeffrey James
• Compton Robert

Classifications

• H01S5/02325

  Mechanically integrated components on mount members or optical micro-benches · CPC title

• G04F5/14 Primary

  using atomic clocks · CPC title

• G04F5/145

  using Coherent Population Trapping · CPC title

• H03L1/04

  Constructional details for maintaining temperature constant · CPC title

• H01S5/183

  having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] · CPC title