TFT substrate and method for making same

Patent metadata

Field	Value
Publication number	US-10749039-B2
Application number	US-201616061653-A
Country	US
Kind code	B2
Filing date	Dec 6, 2016
Priority date	Dec 16, 2015
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

A high-performance TFT substrate ( 100 ) for a flat panel display includes a substrate ( 110 ), a first conductive layer ( 130 ) on the substrate ( 110 ), a semiconductor layer ( 103 ) positioned on the first conductive layer ( 130 ), and a second conductive layer ( 150 ) positioned on the semiconductor layer ( 103 ). The first conductive layer ( 130 ) defines a gate electrode ( 101 ). The second conductive layer ( 150 ) defines a source electrode ( 105 ) and a drain electrode ( 106 ) spaced apart from the source electrode ( 105 ). The second conductive layer ( 150 ) includes a first layer ( 151 ) on the semiconductor layer ( 103 ) and a second layer ( 152 ) positioned on the first layer ( 151 ). The first layer ( 151 ) can be made of metal oxide. The second layer ( 152 ) can be made of aluminum or aluminum alloy.

First claim

The invention claimed is:

1. A TFT substrate comprising:
a substrate;
a semiconductor layer formed on the substrate, the semiconductor layer having a top surface and a bottom surface opposite to and facing away from the top surface;
a first conductive layer formed on the bottom surface of the semiconductor layer, the first conductive layer defining a gate electrode; and
a second conductive layer formed on the top surface of the semiconductor layer opposite to the first conductive layer, the second conductive layer defining a source electrode and a drain electrode spaced apart from the source electrode;
wherein the second conductive layer comprises a first layer positioned on the semiconductor layer, a second layer positioned on the first layer, and a third layer positioned on the second layer; the second layer is made of aluminum; both the third layer and the first layer are made of a same metal oxide; an etching rate of the third layer is greater than an etching rate of the first layer when the second conductive layer is etched by a single etching solution or a single etching gas;
wherein both the third layer and the first layer are made of a same metal oxide containing zinc; the third layer has an atomic percentage of zinc greater than that of the first layer.

2. The TFT substrate of claim 1 , wherein a groove is defined between the source electrode and the drain electrode; the groove extends through the first layer, the second layer, and the third layer; and wherein the size of the groove gradually decreases along a direction from the third layer to the first layer.

3. The TFT substrate of claim 1 , further comprising a gate insulator layer, wherein the gate insulating layer is formed on the substrate and covers the gate electrode; and the semiconductor layer is formed on the gate insulating layer.

4. The TFT substrate of claim 1 , further comprising a passivation layer covering the semiconductor layer and the second conductive layer.

5. The TFT substrate of claim 4 , further comprising a pixel electrode on the passivation layer, wherein the pixel electrode is electrically coupled to the drain electrode.

6. A method for making a TFT substrate comprising:
forming a gate electrode on a substrate;
forming a gate insulating layer on the substrate and covering the gate electrode;
forming a semiconductor layer on the gate insulating layer;
forming a first layer on the semiconductor layer, the first layer being made of a metal oxide;
forming a second layer on the first layer, the second layer being made of aluminum;
forming a third layer on the second layer, the third layer being made of a same metal oxide with the first layer; and
etching the first layer, the second layer, and the third layer to form a source electrode and a drain electrode spaced apart from the source electrode; wherein an etching rate of the third layer is greater than an etching rate of the first layer;
wherein both the third layer and the first layer are made of a same metal oxide containing zinc; and the third layer has an atomic percentage of zinc greater than that of the first layer.

7. The method of claim 6 , wherein a groove is formed between the source electrode and the drain electrode; the groove extends through the first layer, the second layer, and the third layer; and wherein the size of the groove gradually decreases along a direction from the third layer to the first layer.

8. The method of claim 6 , further comprising a step of forming a passivation layer covering the semiconductor layer and the third layer.

Assignees

• Hong Fu Jin Prec Industry (Shenzhen) Co Ltd
• Hon Hai Prec Ind Co Ltd

Inventors

• Kao Yi-Chun
• Shih Po-Li
• Chang Wei-Chih
• Wu I-Wei

Classifications

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10P95/70

  Chemical treatments · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/20

  Dry etching; Plasma etching; Reactive-ion etching · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title