Semiconductor device

Patent metadata

Field	Value
Publication number	US-10748988-B2
Application number	US-201916504858-A
Country	US
Kind code	B2
Filing date	Jul 8, 2019
Priority date	Feb 3, 2017
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

A semiconductor device has an element part and an outer peripheral part, and a deep layer is formed in the outer peripheral part more deeply than a base layer. When a position of the deep layer closest to the element part is defined as a boundary position, a distance between the boundary position and a position closest to the outer peripheral part in an emitter region is defined as a first distance, and a distance between the boundary position and a position of an end of a collector layer is defined as a second distance, the first distance and the second distance are adjusted such that a carrier density in the outer peripheral part is lowered based on breakdown voltage in the outer peripheral part lowered by the deep layer.

First claim

What is claimed is:

1. A semiconductor device having an element part and an outer peripheral part surrounding the element part, comprising:
a semiconductor substrate having a first surface and a second surface opposite to the first surface and forming a drift layer of a first conductive type;
a base layer of a second conductive type disposed on the drift layer in the element part to be adjacent to the first surface of the semiconductor substrate;
a gate insulating film disposed on each wall surface of a plurality of trenches penetrating the base layer to reach the drift layer and extending along a surface direction of the semiconductor substrate;
a gate electrode disposed on the gate insulating film;
an emitter region of the first conductive type disposed on a surface layer of the base layer, the emitter region being in contact with one of the trenches;
a deep layer of the second conductive type disposed on a surface layer of the drift layer in the outer peripheral part to be adjacent the first surface of the semiconductor substrate, the deep layer being deeper than the base layer;
a collector layer of the second conductive type disposed adjacent to the second surface of the semiconductor substrate at least in the element part;
a first electrode electrically connected to the emitter region and the base layer; and
a second electrode electrically connected to the collector layer, wherein
when a predetermined gate voltage is applied to the gate electrode to inject a first carrier in the drift layer from the first electrode via the emitter region and to inject a second carrier in the drift layer from the second electrode via the collector layer, current flows between the first electrode and the second electrode, and
when, on the first surface of the semiconductor substrate, a position of the deep layer closest to the element part is defined as a boundary position, a distance between the boundary position and a position closest to the outer periphery part in the emitter region into which the first carrier is capable of being injected from the first electrode is defined as a first distance, and a distance between the boundary position and a position of an end of the collector layer in the surface direction of the semiconductor substrate is defined as a second distance, the first distance and the second distance are adjusted such that a carrier density in the outer peripheral part is lowered based on a breakdown voltage in the outer peripheral part lowered by the deep layer and are adjusted based on an interval of adjacent two of the trenches,
when a thickness of the semiconductor substrate is defined as a third distance, the second distance is defined as a positive distance in a case where the end of the collector layer is positioned in the element part, the second distance is defined as a negative distance in a case where the end of the collector layer is positioned in the outer peripheral part, the first distance is defined as L 1 , the second distance is defined as L 2 , the third distance is defined as L 3 , and the interval of adjacent two of the trenches is defined as L 4 , the first distance, the second distance, the third distance, and the interval of adjacent two of the trenches satisfy a relationship of L 1 ≥L 3 ×(−0.30×L 4 +1.53)−L 2 .

2. The semiconductor device according to claim 1 , wherein
the first distance, the second distance, the third distance, and the interval of adjacent two of the trenches satisfy a relationship of L 1 =L 3 ×(−0.30×L 4 +1.53)−L 2 .

Assignees

• Denso Corp

Inventors

• Miyata Masanori
• Takahashi Shigeki
• Sumitomo Masakiyo
• Shiga Tomofusa

Classifications

• H10D62/10

  Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D84/641

  Combinations of only vertical BJTs (vertical complementary BJTs H10D84/673) · CPC title

• H10D64/112

  comprising multiple field plate segments · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title