Structure and formation method for chip package

Patent metadata

Field	Value
Publication number	US-10748882-B2
Application number	US-201816126835-A
Country	US
Kind code	B2
Filing date	Sep 10, 2018
Priority date	Oct 13, 2015
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.

First claim

What is claimed is:

1. A method comprising:
forming a conductive feature over a carrier substrate, sidewalls of the conductive feature having a first surface morphology;
heating the conductive feature to change the first surface morphology to a second surface morphology, wherein heating forms an interfacial layer on the sidewalls of the conductive feature;
disposing a semiconductor die adjacent the conductive feature over the carrier substrate; and
after heating the conductive feature, forming a package layer at least partially encapsulating the interfacial layer and the semiconductor die,
wherein the second surface morphology is an undulate morphology.

2. The method of claim 1 , wherein the sidewalls of the conductive feature maintain the second surface morphology before and after forming the package layer.

3. The method of claim 1 further comprising:
forming a redistribution structure electrically connecting the conductive feature and the semiconductor die, wherein the sidewalls of the conductive feature maintain the second surface morphology before and after forming the redistribution structure.

4. The method of claim 3 further comprising:
forming external connectors electrically connected to the redistribution structure, wherein the sidewalls of the conductive feature maintain the second surface morphology before and after forming the external connectors.

5. The method of claim 1 , wherein heating the conductive feature is performed at a temperature of from about 200° C. to about 400° C.

6. The method of claim 1 , wherein heating the conductive feature is performed for a time span of from about 30 minutes to about 2 hours.

7. The method of claim 1 , wherein heating the conductive feature is performed in a nitrogen-containing and oxygen-containing environment having an oxygen concentration of from about 20 ppm to about 100 ppm.

8. The method of claim 1 , wherein the package layer and the interfacial layer have an undulating interface.

9. The method of claim 1 , wherein forming the package layer forms at least one gap between the package layer and the interfacial layer.

10. The method of claim 1 , wherein the first surface morphology is a flat morphology.

11. A method comprising:
forming a conductive feature over a carrier substrate, the conductive feature having a first average grain size;
heating the conductive feature to increase the first average grain size to a second average grain size, wherein heating forms an interfacial layer on sidewalls of the conductive feature; and
after heating the conductive feature, forming a package layer at least partially encapsulating the conductive feature, wherein the conductive feature maintains the second average grain size after forming the package layer.

12. The method of claim 11 further comprising:
disposing a semiconductor die adjacent the conductive feature over the carrier substrate; and
forming the package layer at least partially encapsulating the semiconductor die.

13. The method of claim 12 further comprising:
forming a redistribution structure electrically connecting the conductive feature and the semiconductor die, wherein the conductive feature maintains the second average grain size before and after forming the redistribution structure.

14. The method of claim 13 further comprising:
forming external connectors electrically connected to the redistribution structure, wherein the conductive feature maintains the second average grain size before and after forming the external connectors.

15. The method of claim 11 , wherein the package layer and the interfacial layer share a first undulating interface, and the conductive feature and the interfacial layer share a second undulating interface.

16. The method of claim 11 , wherein the conductive feature is a metal and the interfacial layer is an oxide of the metal.

17. The method of claim 11 , wherein forming the package layer forms at least one gap between the package layer and the interfacial layer.

18. A device comprising:
a package layer; and
a conductive feature extending through the package layer, the conductive feature comprising a metal; and
an interfacial layer around the conductive feature, the interfacial layer comprising an oxide of the metal, the conductive feature and the interfacial layer forming a first interface having an undulating shape, the interfacial layer and the package layer forming a second interface having an undulating shape, the undulating shapes of the first interface and the second interface having a same height variation, a first portion of the interfacial layer contacting the package layer, a second portion of the interfacial layer being physically separated from the package layer.

19. The device of claim 18 further comprising:
a semiconductor die, the package layer at least partially encapsulating the semiconductor die.

20. The device of claim 19 further comprising:
a redistribution structure connecting the semiconductor die to the conductive feature.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hung Jui-Pin
• Huang Cheng-Lin
• Liu Hsien-Wen
• Jeng Shin-Puu

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/073

  of die-attach connectors · CPC title