Phase charge sharing reduction

Patent metadata

Field	Value
Publication number	US-10748600-B2
Application number	US-201816216894-A
Country	US
Kind code	B2
Filing date	Dec 11, 2018
Priority date	Dec 11, 2018
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

Methods, systems, and devices for phase charge sharing are described. In some memory systems or memory devices, one or more decoders may be used to bias access lines of a memory die. The decoders may transfer voltage or current between a first conductive line of the decoder and a second conductive line of the decoder via a shorting device. Transferring the voltage or current may be performed as part of or in association with an operation (e.g., an activate or pre-charge operation) to access one or more memory cells of the memory die. In some examples, the decoders may transfer voltage or current between a first conductive line of a decoder associated with a first refresh activity and a second conductive line of the decoder associated with a second refresh activity via a shorting device.

First claim

What is claimed is:

1. A method, comprising:
applying a first signal to a first conductive line of a row decoder within a bank of a dynamic random access memory (DRAM) array and applying a second signal to a second conductive line of the row decoder within the bank of the DRAM array;
coupling the first conductive line of the row decoder with the second conductive line of the row decoder based at least in part on applying the first signal to the first conductive line and applying the second signal to the second conductive line;
transferring voltage between the first conductive line of the row decoder and the second conductive line of the row decoder based at least in part on coupling the first conductive line with the second conductive line; and
opening or closing one or more rows within the bank of the DRAM array based at least in part on transferring the voltage between the first conductive line of the row decoder and the second conductive line of the row decoder within the bank of the DRAM array.

2. The method of claim 1 , wherein opening or closing the one or more rows within the bank of the DRAM array further comprises:
applying a third signal to an access line coupled with at least one row within the bank of the DRAM array based at least in part on transferring the voltage between the first conductive line and the second conductive line.

3. The method of claim 1 , further comprising:
applying the second signal to the first conductive line of the row decoder and applying the first signal to the second conductive line of the row decoder after coupling the first conductive line with the second conductive line, wherein opening or closing the one or more rows is based at least in part on applying the second signal to the first conductive line and applying the first signal to the second conductive line.

4. The method of claim 3 , further comprising:
decoupling the first conductive line of the row decoder from the second conductive line of the row decoder after transferring the voltage between the first conductive line and the second conductive line for a period of time, wherein applying the second signal to the first conductive line and applying the first signal to the second conductive line is based at least in part on the decoupling.

5. The method of claim 1 , further comprising:
decoupling the first conductive line of the row decoder from a source of the first signal; and
decoupling the second conductive line of the row decoder from a source of the second signal, wherein coupling the first conductive line with the second conductive line is based at least in part on decoupling the first conductive line from the source of the first signal and decoupling the second conductive line from the source of the second signal.

6. The method of claim 1 , wherein transferring the voltage between the first conductive line of the row decoder and the second conductive line of the row decoder occurs as at least part of an activate operation or a precharge operation, and the second signal is a complement of the first signal.

7. A method, comprising:
applying a first signal to a first conductive line of a row decoder within a bank of a dynamic random access memory (DRAM) array;
opening or closing a first set of rows within the bank of the DRAM array based at least in part on applying the first signal to the first conductive line of the row decoder;
coupling the first conductive line with a second conductive line of the row decoder based at least in part on applying the first signal to the first conductive line of the row decoder;
transferring voltage between the first conductive line of the row decoder and the second conductive line of the row decoder based at least in part on coupling the first conductive line with the second conductive line;
applying the first signal to the second conductive line of the row decoder based at least in part on transferring the voltage between the first conductive line and the second conductive line; and
opening or closing a second set of rows within the bank of the DRAM array based at least in part on applying the first signal to the second conductive line of the row decoder.

8. The method of claim 7 , further comprising:
decoupling the first conductive line from the second conductive line of the row decoder before applying the first signal to the second conductive line of the row decoder.

9. The method of claim 7 , wherein transferring the voltage between the first conductive line of the row decoder and the second conductive line of the row decoder occurs between opening or closing the first set of rows and opening or closing the second set of rows.

10. The method of claim 7 , wherein transferring the voltage between the first conductive line of the row decoder and the second conductive line of the row decoder occurs between refresh operations.

11. A method, comprising:
applying a first signal to a first conductive line of a row decoder within a bank of a dynamic random access memory (DRAM) array;
opening or closing a first set of rows within the bank of the DRAM array based at least in part on applying the first signal to the first conductive line of the row decoder;
decoupling the first conductive line of the row decoder from a source of the first signal;
decoupling a second conductive line of the row decoder from a source of a second signal, the second signal being a complement of the first signal;
coupling the first conductive line with the second conductive line of the row decoder based at least in part on applying the first signal to the first conductive line of the row decoder, decoupling the first conductive line from the source of the first signal, and decoupling the second conductive line from the source of the second signal;
transferring voltage between the first conductive line of the row decoder and the second conductive line of the row decoder based at least in part on coupling the first conductive line with the second conductive line;
applying the first signal to the second conductive line of the row decoder based at least in part on transferring the voltage between the first conductive line and the second conductive line; and
opening or closing a second set of rows within the bank of the DRAM array based at least in part on applying the first signal to the second conductive line of the row decoder.

12. A method, comprising:
applying a first signal to a first conductive line of a row decoder within a bank of a dynamic random access memory (DRAM) array;
applying a second signal to a third conductive line of the row decoder, the second signal being a complement of the first signal;
opening or closing a first set of rows within the bank of the DRAM array based at least in part on applying the first signal to the first conductive line of the row decoder and applying the second signal to the third conductive line of the row decoder;
coupling the first conductive line with a second conductive line of the row decoder based at least in part on applying the first signal to the first conductive line of the row decoder;
transferring voltage between the first conductive line of the row decoder and the second conductive line of the row decoder based at least in part on coupling the first conductive line with the second conductive line;
applying the first signal to the second conductive line of the row decoder based at least in part on transferring the voltage between the first conductive line and the second conductive line;
coupling the third conductive line with a fourth conductive line of the row decoder based at least in part on applying the second signal;
transferring a second voltage between the third conductive line o

Assignees

• Micron Technology Inc
• Micron Technologies Inc

Inventors

• Rehmeyer James S
• Raad George B
• Bell Debra M
• Geiger Markus H
• Veches Anthony D

Classifications

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C11/4087 Primary

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• G11C11/2257

  Word-line or row circuits · CPC title

• G11C11/2293

  Timing circuits or methods · CPC title

• G11C11/2259

  Cell access · CPC title