Full screen processing in multi-application environments

Patent metadata

Field	Value
Publication number	US-10748233-B2
Application number	US-201113578355-A
Country	US
Kind code	B2
Filing date	Jun 11, 2011
Priority date	Jun 14, 2011
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

Systems and methods for determining a foreground application and at least one background application from multiple graphics applications executing within an execution environment are disclosed. Pixel data rendered by the foreground application may be displayed in the execution environment while a rendering thread of the background application may be paused.

First claim

What is claimed:

1. A method, comprising:
at one or more processor cores,
determining, for a plurality of graphics applications executing within an execution environment, a foreground application and at least one background application;
providing pixel data rendered by the foreground application in the execution environment; and
pausing rendering processes of the background application while continuing rendering processes of the foreground application to provide the pixel data in response to an instruction to perform a switch between rendering to a foreground and rendering to a background.

2. The method of claim 1 , wherein the pixel data comprises pixel data rendered for full screen display by the execution environment.

3. The method of claim 1 , wherein determining a foreground application comprises intercepting a flip call.

4. The method of claim 1 , wherein providing the pixel data comprises performing a native flip for a rendering process of the foreground application.

5. The method of claim 4 , further comprising:
disabling the native flip for the rendering process of the foreground application; and
resuming the rendering processes of the background application.

6. The method of claim 1 , wherein determining a foreground application comprises providing information associated with the foreground application to an application registry.

7. The method of claim 1 , wherein determining a foreground application comprises detecting an underlying memory surface.

8. The method of claim 7 , wherein determining a foreground application comprises providing information associated with the memory surface to a graph library.

9. The method of claim 8 , wherein providing information associated with the memory surface to the graph library comprises using an agent associated with the foreground application to provide information associated with the memory surface to the graph library.

10. A system, comprising:
memory to store a plurality of graphics applications; and
one or more processor cores coupled to the memory, wherein the one or more processor cores are configured to determine, for the plurality of graphics applications, a foreground application and at least one background application, to provide pixel data rendered by the foreground application, and, while continuing rendering processes of the foreground application to provide the pixel data, to pause rendering processes of the background application in response to an instruction to perform a switch between rendering to a foreground and rendering to a background.

11. The system of claim 10 , wherein each graphics application comprises a graphics wrapper, and wherein the one or more processor cores are configured to determine the foreground application in response to information received from a graphics wrapper of the foreground application.

12. The system of claim 11 , wherein information received from the graphics wrapper of the foreground application comprises memory surface information.

13. The system of claim 10 , wherein the one or more processor cores are configured to determine a foreground application by intercepting a flip call.

14. The system of claim 10 , wherein the one or more processor cores are configured to provide the pixel data by performing a native flip for a rendering process of the foreground application.

15. An article comprising a computer program product having stored therein instructions that, if executed, result in:
at one or more processor cores,
determining, for a plurality of graphics applications executing within an execution environment, a foreground application and at least one background application;
providing pixel data rendered by the foreground application in the execution environment; and
pausing rendering processes of the background application while continuing rendering processes of the foreground application to provide the pixel data application in response to an instruction to perform a switch between rendering to a foreground and rendering to a background.

16. The article of claim 15 , wherein instructions for determining a foreground application include instructions for intercepting a flip call.

17. The article of claim 15 , wherein instructions for providing the pixel data include instructions for performing a native flip for a rendering process of the foreground application.

18. The article of claim 15 , wherein instructions for determining a foreground application include instructions for detecting an underlying memory surface.

19. The article of claim 18 , wherein instructions for determining a foreground application include instructions for providing information associated with the memory surface to a graph library.

20. The article of claim 19 , wherein instructions for providing information associated with the memory surface to the graph library include instructions for using an agent associated with the foreground application to provide information associated with the memory surface to the graph library.

Assignees

• Zhao Tao
• Weast John C
• Wang Brett P
• Intel Corp

Inventors

• Zhao Tao
• Weast John C
• Wang Brett P

Classifications

• G06F9/485 Primary

  Task life-cycle, e.g. stopping, restarting, resuming execution (G06F9/4881 takes precedence) · CPC title

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F9/451

  Execution arrangements for user interfaces · CPC title