Cache management system and method

Patent metadata

Field	Value
Publication number	US-10747674-B2
Application number	US-201816034657-A
Country	US
Kind code	B2
Filing date	Jul 13, 2018
Priority date	Jul 31, 2017
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

A method, computer program product, and computing system for identifying, at the computing device, one or more cache pages in a cache system. One or more cache pages may be refactored into one or more cache units within the one or more cache pages. A plurality of parallel IO requests may be executed on the one or more cache units within the one or more cache pages.

First claim

What is claimed is:

1. A computer-implemented method, executed on a computing device, comprising:
identifying, at the computing device, one or more cache pages in a cache system;
refactoring the one or more cache pages into one or more cache units within each of the one or more cache pages based upon, at least in part, an alignment pattern of a plurality of parallel IO requests relative to a length of the one or more cache pages, wherein the alignment pattern of the plurality of parallel IO requests is defined by the plurality of parallel IO requests having an offset and a length that are each a multiple of an alignment length, wherein refactoring the one or more cache pages into one or more cache units within the one or more cache pages includes defining the one or more cache units as portions within each of the one or more cache pages with the alignment length, wherein refactoring the one or more cache pages includes generating one or more bitmaps for the one or cache pages, wherein one or more bits in the one or more bitmaps represent the one or more cache units within the one or more cache pages and wherein the number of bits in the one or more bitmaps is based upon, at least in part, the length of the one or more cache units; and
executing the plurality of parallel IO requests on the one or more cache units within the one or more cache pages.

2. The computer implemented method of claim 1 , wherein executing the plurality of parallel IO requests includes:
locking at least one cache unit of the one or more cache units within the one or more cache pages during execution of the plurality of parallel IO requests on the at least one cache unit.

3. The computer-implemented method of claim 1 , wherein the one or more bits in the one or more bitmaps indicate which cache units within the one or more cache pages are valid.

4. The computer-implemented method of claim 1 , wherein the one or more bits in the one or more bitmaps indicate which cache units within the one or more cache pages are dirty.

5. The computer-implemented method of claim 4 , further comprising:
flushing one or more dirty cache units of the one or more cache units within the one of more cache pages based upon, at least in part, the one or more bits in the one or more bitmaps which indicate which cache units within the one or more cache pages are dirty.

6. A computer program product residing on a non-transitory computer readable medium having a plurality of instructions stored thereon which, when executed by a processor, cause the processor to perform operations comprising:
identifying one or more cache pages in a cache system;
refactoring the one or more cache pages into one or more cache units within each of the one or more cache pages based upon, at least in part, an alignment pattern of a plurality of parallel IO requests relative to a length of the one or more cache pages wherein the alignment pattern of the plurality of parallel IO requests is defined by the plurality of parallel IO requests having an offset and a length that are each a multiple of an alignment length, wherein refactoring the one or more cache pages into one or more cache units within the one or more cache pages includes defining the one or more cache units as portions within each of the one or more cache pages with the alignment length, wherein refactoring the one or more cache pages includes generating one or more bitmaps for the one or cache pages, wherein one or more bits in the one or more bitmaps represent the one or more cache units within the one or more cache pages and wherein the number of bits in the one or more bitmaps is based upon, at least in part, the length of the one or more cache units; and
executing the plurality of parallel IO requests on the one or more cache units within the one or more cache pages.

7. The computer program product of claim 6 , wherein executing the plurality of parallel IO requests includes:
locking at least one cache unit of the one or more cache units within the one or more cache pages during execution of the plurality of parallel IO requests on the at least one cache unit.

8. The computer program product of claim 6 , wherein the one or more bits in the one or more bitmaps indicate which cache units within the one or more cache pages are valid.

9. The computer program product of claim 6 , wherein the one or more bits in the one or more bitmaps indicate which cache units within the one or more cache pages are dirty.

10. The computer program product of claim 9 , further comprising instructions for:
flushing one or more dirty cache units of the one or more cache units within the one of more cache pages based upon, at least in part, the one or more bits in the one or more bitmaps which indicate which cache units within the one or more cache pages are dirty.

11. A computing system including a processor and memory configured to perform operations comprising:
identifying one or more cache pages in a cache system;
refactoring the one or more cache pages into one or more cache units within each of the one or more cache pages based upon, at least in part, an alignment pattern of a plurality of parallel IO requests relative to a length of the one or more cache pages wherein the alignment pattern of the plurality of parallel IO requests is defined by the plurality of parallel IO requests having an offset and a length that are each a multiple of an alignment length, wherein refactoring the one or more cache pages into one or more cache units within the one or more cache pages includes defining the one or more cache units as portions within each of the one or more cache pages with the alignment length, wherein refactoring the one or more cache pages includes generating one or more bitmaps for the one or cache pages, wherein one or more bits in the one or more bitmaps represent the one or more cache units within the one or more cache pages and wherein the number of bits in the one or more bitmaps is based upon, at least in part, the length of the one or more cache units; and
executing the plurality of parallel IO requests on the one or more cache units within the one or more cache pages.

12. The computing system of claim 11 , wherein executing the plurality of parallel IO requests includes:
locking at least one cache unit of the one or more cache units within the one or more cache pages during execution of the plurality of parallel IO requests on the at least one cache unit.

13. The computing system of claim 11 , wherein the one or more bits in the one or more bitmaps indicate which cache units within the one or more cache pages are dirty.

14. The computing system of claim 13 , further configured to perform operations comprising:
flushing one or more dirty cache units of the one or more cache units within the one of more cache pages based upon, at least in part, the one or more bits in the one or more bitmaps which indicate which cache units within the one or more cache pages are dirty.

Assignees

• Emc Ip Holding Co Llc
• Emc Ip Holding Co Llc

Inventors

• Hu Wilson
• Zhou Qiaosheng
• Lv Shuo

Classifications

• G06F12/0844 Primary

  Multiple simultaneous or quasi-simultaneous cache accessing · CPC title

• G06F12/0895

  of parts of caches, e.g. directory or tag array · CPC title

• G06F12/0893

  Caches characterised by their organisation or structure · CPC title

• G06F12/0866

  for peripheral storage systems, e.g. disk cache · CPC title

• G06F12/0884 Primary

  Parallel mode, e.g. in parallel with main memory or CPU · CPC title