Reducing disturbance between adjacent regions of a memory device

Patent metadata

Field	Value
Publication number	US-10747448-B2
Application number	US-201715598446-A
Country	US
Kind code	B2
Filing date	May 18, 2017
Priority date	Sep 29, 2016
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

A memory system includes a memory device including one or more memory blocks, and configured to store data in a plurality of pages included in each memory block through a write operation, and a memory controller configured to count an operation number of write operations performed on the memory block, check whether the write operation is performed for each of the pages, select one or more victim pages among the pages, and copy data stored in the victim pages.

First claim

What is claimed is:

1. A memory system comprising:
a memory device including one or more memory blocks, and configured to store data in a plurality of pages included in each memory block through a write operation; and
a memory controller configured to count an operation number of write operations performed on each memory block and check whether a write operation is performed for each of the pages to generate a code value according to a result of the check, wherein the code value includes a plurality of bit values respectively corresponding to the pages in each memory block, each bit value being enabled when a write operation is performed to a corresponding page,
wherein, when a memory block has the counted operation number of write operations exceed a first threshold value, the memory controller selects a page checked with the write operation being performed and a page adjacent to the checked page as one or more victim pages, among the pages of the memory block, and copies data stored in the victim pages,
wherein the memory controller comprises:
a write operation counting unit configured to first count the operation number of write operations performed on the memory block and enable a count signal when the first counted operation number of write operations exceeds the first threshold value;
a write operation check unit configured to check whether the write operation is performed for each of the pages and output the code value according to the result of the check: and
a scrub operation determination unit configured to determine whether a scrub operation is performed to the memory block based on the count signal and the code value.

2. The memory system of claim 1 , wherein the scrub operation determination unit selects as the victim page, when the count signal is enabled, a page corresponding to an enabled bit value of the code value and a page adjacent thereto.

3. The memory system of claim 1 , wherein, when all of the bit values of the code value are enabled, the write operation check unit initializes the enabled bit values and enables a dirty page signal.

4. The memory system of claim 3 , wherein the write operation counting unit second counts the operation number of write operations performed while all of the bit values of the code value are enabled, and compares the second counted operation number of write operations with a second threshold value when the dirty page signal is enabled.

5. The memory system of claim 4 , wherein, when the second counted operation number of write operations is the same as the second threshold value, the write operation counting unit initializes the first counted operation number of write operations.

6. The memory system of claim 5 , wherein the second threshold value refers to the number of the pages included in the memory block.

7. An operating method for a memory system, comprising:
first counting an operation number of write operations performed on one or more memory blocks included in a memory device;
checking, among a plurality of pages included in each memory block, a page on which a write operation is performed to generate a code value according to a result of the checking, wherein the code value includes a plurality of bit values respectively corresponding to the pages in each memory block, each bit value being enabled when a write operation is performed to a corresponding page;
selecting, when a memory block has the first counted operation number of write operations exceed a first threshold value, a page checked with the write operation being performed and a page adjacent to the checked page as one or more victim pages among the pages of the memory block, based on a result of the checking;
copying data stored in the selected victim pages;
second counting the operation number of write operations while all of the pages included in the memory block are checked as a result of the checking:
comparing the second counted operation number of write operations with a second threshold value; and
resetting the first counted operation number of write operations when the second counted operation number of write operations is the same as a second threshold value.

8. The operating method of claim 7 , wherein the selecting of the victim pages comprises:
comparing the first counted operation number of write operations with the first threshold value; and
selecting, when the first counted operation number of write operations exceeds the first threshold value as a result of the comparing, the checked page and the page adjacent to the checked page as the victim pages.

9. The operating method of claim 7 , further comprising, when all of the pages included in the memory block are checked as a result of the checking, resetting the result of the checking.

10. The operating method of claim 7 , wherein the second threshold value refers to the number of the pages included in the memory block.

Assignees

• Sk Hynix Inc

Inventors

• Kwon Jung-Hyun
• JO Sang-Gu
• Hong Do-Sun

Classifications

• G06F11/106 Primary

  Correcting systematically all correctable errors, i.e. scrubbing · CPC title

• G11C7/02

  with means for avoiding parasitic signals · CPC title

• G11C13/0035

  Evaluating degradation, retention or wearout, e.g. by counting writing cycles · CPC title

• G11C13/0033

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title