Card and host apparatus

Patent metadata

Field	Value
Publication number	US-10747299-B2
Application number	US-201916564441-A
Country	US
Kind code	B2
Filing date	Sep 9, 2019
Priority date	Dec 27, 2004
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus.

First claim

What is claimed is:

1. A memory system comprising a host apparatus connectable to a memory device which comprises a memory core and a memory controller, the host apparatus configured to:
send a first command to the memory device,
receive a response transmitted from the memory device, in response to the first command, the response including status data that is used to determine whether the memory device supports a termination process, the termination process including shifting into a state ready for a stop of power supply from the host apparatus,
send a function stop command to the memory device so that the memory device performs the termination process in response to the function stop command,
receive a first signal while performing the termination process, the first signal being indicative of a busy state and having a first level, and
receive as a notification of a completion of the busy state, a second signal being indicative of a ready state and having a second level when the memory device completes the termination process.

2. The memory system according to claim 1 , wherein the termination process includes writing data stored in a volatile semiconductor memory into the memory core.

3. The memory system according to claim 1 , wherein the memory system is configured to change information to indicate that the termination process has not been completed when a status of the memory system has changed since completion of a latest initialization.

4. The memory system according to claim 1 , wherein the memory system is configured to:
receive an initialization command instructing to carry out initialization,
execute initialization using a first initialization method when information indicates that the termination process has not been completed, and
execute initialization using a second initialization method, which is finished quicker than the first initialization method, when the memory core indicates that the termination process has been completed.

5. The memory system according to claim 4 , wherein the second initialization method comprises the first initialization method with a part of it omitted.

6. The memory system according to claim 5 , wherein the omitted part includes at least one of checking for errors of data stored in the memory core, restoring the errors, and constructing a translation table showing a relation between logical addresses of write data and physical addresses of the memory core which stores the write data.

Assignees

• Toshiba Memory Corp

Inventors

• Fujimoto Akihisa

Classifications

• G06F3/08

  from or to individual record carriers, e.g. punched card {, memory card, integrated circuit [IC] card or smart card} · CPC title

• B42D25/305

  Associated digital information (record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00) · CPC title

• G06K19/07 Primary

  with integrated circuit chips · CPC title

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06K19/07732

  the record carrier having a housing or construction similar to well-known portable memory devices, such as SD cards, USB or memory sticks (housings for electrical equipment in general, see H05K5/02) · CPC title