Display panel, method for making the same and method for controlling the same

Patent metadata

Field	Value
Publication number	US-10747076-B2
Application number	US-201815751945-A
Country	US
Kind code	B2
Filing date	Jan 2, 2018
Priority date	Nov 29, 2017
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

The disclosure provides a display panel, a method for making the display panel, and a method for controlling the display panel. The display panel comprises: multiple gate lines and multiple data line crossing the multiple gate lines to form multiple pixel regions; multiple pixel electrodes in the multiple pixel regions; multiple first thin film transistors in the multiple pixel regions, the gates of the multiple first thin film transistors are connected to the gate lines, and the sources and the drains are connected to the data lines and the pixel electrodes respectively; and a second thin film transistor between and connecting two adjacent pixel electrodes, wherein the second thin film transistor is in a non-conducting state when the display panel is under normal operation, and the second thin film transistor is in a conducting state when the display panel is under a power failure condition.

First claim

What is claimed is:

1. A display panel, comprising
multiple gate lines and multiple data line crossing the multiple gate lines to form multiple pixel regions;
multiple pixel electrodes in the multiple pixel regions;
multiple first thin film transistors in the multiple pixel regions, wherein each of the multiple first thin film transistors comprises a gate, source and a drain, the gates of the multiple first thin film transistors are connected to the gate lines, and the sources and the drains are connected to the data lines and the pixel electrodes respectively; and
multiple second thin film transistors, wherein each of the second thin film transistors is between and connecting two adjacent pixel electrodes, the second thin film transistor is in a non-conducting state when the display panel is under normal operation, and the second thin film transistor is in a conducting state to make the two adjacent pixel electrodes driven by opposite charges release charges through the second thin film transistor when the display panel is under a power failure condition caused by that the display panel shuts down unexpectedly.

2. The display panel according to claim 1 , further comprising multiple global signal lines, wherein each of the global signal lines is between two adjacent gate lines and electrically connected with more than one of the second thin film transistors in a transverse direction, the second thin film transistor comprises a gate connected to the global signal line, the second thin film transistor further comprises a source and a drain connected to the two adjacent pixel electrodes arranged in the transverse direction and adjacent to the second thin film transistor respectively, and the second thin film transistors electrically connected with different ones of the global signal lines all are in conducting states in a period of time when the display panel is under the power failure condition.

3. The display panel according to claim 2 , wherein when the display panel is under normal operation, a voltage that the global signal line applied to the gate of the second thin film transistor is VGL (voltage gate low), and when the display panel is under the power failure condition, the voltage that the global signal line applied to the gate of the second thin film transistor is VGH (voltage gate high) and maintains for the period of time.

4. The display panel according to claim 3 , wherein after the voltage that the global signal line applied to the gate of the second thin film transistor is voltage gate high and maintains for the period of time, the pixel regions in the display panel are at lower positive potentials with a same charge amount, at lower negative potentials with a same charge amount, or at a same ground potential (GND).

5. The display panel according to claim 1 , wherein the second thin film transistor is an n-type thin film transistor.

6. A method for making a display panel, comprising:
disposing multiple gate lines and multiple data line on a substrate, wherein the multiple data line cross the multiple gate lines to form multiple pixel regions;
disposing multiple first thin film transistors and multiple pixel electrodes in the multiple pixel regions, wherein each of the multiple first thin film transistors comprises a gate, source and a drain, connecting the gates of multiple first thin film transistors to the gate lines, and connecting the sources and the drains of the multiple first thin film transistor to the gate lines and the data lines respectively;
disposing multiple second thin film transistors, wherein each of the second thin film transistors is between two adjacent pixel electrodes, the second thin film transistor is in a non-conducting state when the display panel is under normal operation, and the second thin film transistor is in a conducting state to make the two adjacent pixel electrodes driven by opposite charges release charges through the second thin film transistor when the display panel is under a power failure condition caused by that the display panel shuts down unexpectedly.

7. The method according to claim 6 , further comprising: disposing multiple global signal lines, wherein each of the global signal lines is between two adjacent gate lines and electrically connected with more than one of the second thin film transistors in a transverse direction; connecting a gate of the second thin film transistor to the global signal line, and connecting a source and a drain of the second thin film transistor to the two adjacent pixel electrodes arranged in the transverse direction and adjacent to the second thin film transistor respectively; wherein the second thin film transistors electrically connected with different ones of the global signal lines all are in conducting states in a period of time when the display panel is under the power failure condition.

8. A method for controlling a display panel, wherein the display panel comprises multiple gate lines and multiple data line crossing the multiple gate lines to form multiple pixel regions; multiple pixel electrodes in the multiple pixel regions; multiple first thin film transistors in the multiple pixel regions, wherein each of the multiple first thin film transistors comprises a gate, source and a drain, the gates of multiple first thin film transistors are connected to the gate lines, and the sources and the drains are connected to the data lines and the pixel electrodes respectively; multiple second thin film transistors, wherein each of the second thin film transistors is between and connecting two adjacent pixel electrodes arranged in a transverse direction; and multiple global signal lines, wherein each of the global signal lines is between two adjacent gate lines and electrically connected with more than one of the second thin film transistors in the transverse direction, wherein the method comprises:
the second thin film transistor is in a non-conducting state when the display panel is under normal operation, and the second thin film transistors electrically connected with different ones of the global signal lines all are in conducting states in a period of time when the display panel is under a power failure condition.

9. The method according to claim 8 , wherein the second thin film transistor further comprises a source and a drain connected to the two adjacent pixel electrodes adjacent to the second thin film transistor respectively, the method further comprises: when the display panel is under normal operation, the global signal line applies a voltage gate low (VGL) to the gate of the second thin film transistor, and when the display panel is under the power failure condition caused by that the display panel shuts down unexpectedly, the global signal line applies a voltage gate high to the gate of the second thin film transistor for the period of time.

10. The method according to claim 9 , wherein after the voltage that the global signal line applied to the gate of the second thin film transistor is voltage gate high and maintains for the period of time, the pixel regions in the display panel are at lower positive potentials with a same charge amount, at lower negative potentials with a same charge amount, or at a same ground potential (GND).

Assignees

• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Hong Guanghui
• Gong Qiang

Classifications

• G02F1/136245

  having complementary transistors · CPC title

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title

• G09G3/3648

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09G3/3688

  suitable for active matrices only · CPC title

• G09G3/3614 Primary

  Control of polarity reversal in general · CPC title