Method and device for embedding flash memory and logic integration in FinFET technology

Patent metadata

Field	Value
Publication number	US-10741552-B2
Application number	US-201816040105-A
Country	US
Kind code	B2
Filing date	Jul 19, 2018
Priority date	Jun 23, 2017
Publication date	Aug 11, 2020
Grant date	Aug 11, 2020

Abstract

Methods for preventing step-height difference of flash and logic gates in FinFET devices and related devices are provided. Embodiments include forming fins in flash and logic regions; recessing an oxide exposing an upper portion of the fins; forming an oxide liner over the upper portion in the flash region; forming a polysilicon gate over and perpendicular to the fins in both regions; removing the gate from the logic region and patterning the gate in the flash region forming a separate gate over each fin; forming an ONO layer over the gates in the flash region; forming a second polysilicon gate over and perpendicular to the fins in both regions; planarizing the second polysilicon gate exposing a portion of the ONO layer over the gates in the flash region; forming and patterning a hardmask, exposing STI regions between the flash and logic regions; and forming an ILD over the STI regions.

First claim

What is claimed is:

1. A device comprising:
silicon (Si) fins formed in flash and logic regions of a substrate;
an oxide liner formed over an upper portion of the fins in the flash region;
a first polysilicon gate and a second polysilicon gate formed over the oxide liner in the flash region;
an oxide nitride oxide (ONO) layer formed over the first and second polysilicon gates in the flash region, wherein the ONO continuously extends between the first polysilicon gate and the second polysilicon gate in the flash region when viewed in cross section;
a control gate formed between the first and second polysilicon gates in the flash region; and
a metal gate formed over the fins in the logic region,
wherein the first and second polysilicon gates in the flash region are flash gates and they share the control gate.

2. The device according to claim 1 , wherein the first and second polysilicon gates in the flash region are coplanar with the control gate in the flash region.

3. The device according to claim 2 , wherein the control gate is formed of polysilicon and is self-aligned between the first and second polysilicon gates in the flash region.

4. The device according to claim 3 , wherein the polysilicon control gate is formed over a portion of the ONO layer between the first and second polysilicon gates in the flash region.

5. The device according to claim 1 , wherein the first and second polysilicon gates in the flash region are coplanar with the control gate in the flash region.

6. The device according to claim 5 , wherein the control gate is formed of metal and is self-aligned between the first and second polysilicon gates in the flash region.

7. The device according to claim 6 , wherein the metal control gate is formed over a high-k dielectric layer and a portion of the ONO layer between the first and second polysilicon gates in the flash region.

8. A device comprising:
fins formed in flash and logic regions of a substrate;
an oxide liner formed over an upper portion of the fins in the flash region;
a first polysilicon flash gate and a second polysilicon flash gate formed over the oxide liner in the flash region;
an oxide nitride oxide (ONO) layer formed over the first and second polysilicon flash gates in the flash region, wherein the ONO continuously extends between the first polysilicon flash gate and the second polysilicon flash gate when viewed in cross section;
a control gate formed between the first and second polysilicon flash gates in the flash region; and
a metal gate formed over the fins in the logic region.

9. The device according to claim 8 , wherein the first and second polysilicon flash gates share the control gate.

10. The device according to claim 8 , wherein the first and second polysilicon gates in the flash region are coplanar with the control gate in the flash region.

11. The device according to claim 10 , wherein the control gate is formed of polysilicon and is self-aligned between the first and second polysilicon gates in the flash region.

12. The device according to claim 11 , wherein the polysilicon control gate is formed over a portion of the ONO layer between the first and second polysilicon gates in the flash region.

13. The device according to claim 8 , wherein the first and second polysilicon gates in the flash region are coplanar with the control gate in the flash region.

14. The device according to claim 13 , wherein the control gate is formed of metal and is self-aligned between the first and second polysilicon gates in the flash region.

15. The device according to claim 14 , wherein the metal control gate is formed over a high-k dielectric layer and a portion of the ONO layer between the first and second polysilicon gates in the flash region.

16. A device comprising:
a first polysilicon flash gate and a second polysilicon flash gate formed in a flash region;
an oxide nitride oxide (ONO) layer formed over the first and second polysilicon flash gates in the flash region;
a control gate formed between the first and second polysilicon flash gates in the flash region; and
a metal gate formed in the logic region,
wherein the ONO continuously extends between the first polysilicon flash gate and the second polysilicon flash gate when viewed in cross section.

17. The device according to claim 16 , wherein the first and second polysilicon flash gates, control gate and metal gate are formed over silicon fins.

18. The device according to claim 17 , further comprising:
an oxide liner formed over an upper portion of the silicon fins in the flash region.

19. The device according to claim 16 , wherein:
the polysilicon control gate is formed over a portion of the ONO layer between the first and second polysilicon flash gates in the flash region,
the first and second polysilicon flash gates in the flash region are coplanar with the control gate in the flash region, and
the control gate is formed of metal and is self-aligned between the first and second polysilicon flash gates in the flash region.

20. The device according to claim 19 , wherein the metal control gate is formed over a high-k dielectric layer and a portion of the ONO layer between the first and second polysilicon flash gates in the flash region.

Assignees

• Globalfoundries Sg Pte Ltd
• Globalfounders Singapore Pte Ltd

Inventors

• Zhu Ming
• Li Pinghui
• Yeow Su Yi Susan
• Nga Yiang Aun
• Shum Danny Pak-Chum
• Toh Eng Huat

Classifications

• H10P14/6526

  introduced into an oxide material, e.g. changing SiO to SiON · CPC title

• H10P14/6522

  introduced into a nitride material, e.g. changing SiN to SiON · CPC title

• H10D84/834 Primary

  comprising FinFETs · CPC title

• H10D62/113

  Isolations within a component, i.e. internal isolations · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title