Modifying circuits to prevent redundant switching

Patent metadata

Field	Value
Publication number	US-10740516-B2
Application number	US-201815970979-A
Country	US
Kind code	B2
Filing date	May 4, 2018
Priority date	May 4, 2018
Publication date	Aug 11, 2020
Grant date	Aug 11, 2020

Abstract

An unobservable cycle for at least one latch in a circuit design is detected. The unobservable cycle indicates that the at least one latch is not observable to downstream logic in the circuit design. A coverage event is generated to identify the unobservable cycle for the at least one latch. The coverage event is tracked to detect a state associated with the unobservable cycle and a state change cycle. The state change cycle is determined based on a simulation technique. A redundant switching of the at least one latch based on the state associated with the unobservable cycle and the state change cycle is determined. Furthermore, manufacturing of a circuit based on the circuit design is at least initiated. The circuit design is modified to prevent the redundant switching of the at least one latch.

First claim

What is claimed is:

1. A system to facilitate manufacturing of circuits comprising:
at least one processor to perform a method, the method comprising:
detecting an unobservable cycle for at least one latch in a circuit design, wherein the unobservable cycle indicates that the at least one latch is not observable to downstream logic in the circuit design;
generating a coverage event to identify the unobservable cycle for the at least one latch;
tracking the coverage event to detect a state associated with the unobservable cycle and a state change cycle, wherein the state change cycle is determined based on a simulation technique, and wherein the state change cycle comprises a cycle in which the at least one latch changes a value from a previous state;
determining a redundant switching of the at least one latch based on the state associated with the unobservable cycle and the state change cycle; and
initiating manufacturing of a circuit based on the circuit design, wherein the circuit design is modified to prevent the redundant switching of the at least one latch based in part on the unobservable cycle.

2. The system of claim 1 , wherein the method further comprises generating an auxiliary latch associated with the at least one latch, wherein the auxiliary latch stores a previous value of the at least one latch.

3. The system of claim 1 , wherein the unobservable cycle is based on a set of fanout points associated with the at least one latch.

4. The system of claim 1 , wherein the detecting comprises detecting the unobservable cycle based on a set of sequential signals from interconnected computation logic.

5. The system of claim 1 , wherein the coverage event comprises a plurality of signals to be monitored.

6. The system of claim 1 , wherein the at least one latch is coupled to a multiplexer that receives a first signal from an array or a second signal from computation logic.

7. The system of claim 6 , wherein the circuit design that is modified comprises logic to prevent power to the multiplexer in a condition in which the second signal is unobservable.

8. The system of claim 1 , wherein the detecting further comprises detecting the unobservable cycle for the at least one latch in the circuit design via a formal verification technique.

9. The system of claim 1 , wherein the generating further comprises generating the coverage event to identify the unobservable cycle for the at least one latch based on a formal verification technique.

10. A computer-implemented method to facilitate manufacturing of circuits comprising:
detecting an unobservable cycle for at least one latch in a circuit design, wherein the unobservable cycle indicates that the at least one latch is not observable to downstream logic in the circuit design;
generating a coverage event to identify the unobservable cycle for the at least one latch;
tracking the coverage event to detect a state associated with the unobservable cycle and a state change cycle, wherein the state change cycle is determined based on a simulation technique, and wherein the state change cycle comprises a cycle in which the at least one latch changes values from a previous state;
determining a redundant switching of the at least one latch based on the state associated with the unobservable cycle and the state change cycle; and
initiating manufacturing of a circuit based on the circuit design, wherein the circuit design is modified to prevent the redundant switching of the at least one latch based in part on the unobservable cycle, and wherein the detecting, generating, tracking, determining and initiating are performed using at least one processor.

11. The computer-implemented method of claim 10 , further comprising generating an auxiliary latch associated with the at least one latch, wherein the auxiliary latch stores a previous value of the at least one latch.

12. The computer-implemented method of claim 10 , wherein the unobservable cycle is based on a set of fanout points associated with the at least one latch.

13. The computer-implemented method of claim 10 , wherein the detecting comprises detecting the unobservable cycle based on a set of sequential signals from interconnected computation logic.

14. The computer-implemented method of claim 10 , wherein the coverage event comprises a plurality of signals to be monitored.

15. The computer-implemented method of claim 10 , wherein the at least one latch is coupled to a multiplexer that receives a first signal from an array or a second signal from computation logic.

16. The computer-implemented method of claim 15 , wherein the circuit design that is modified comprises logic to prevent power to the multiplexer in a condition in which the second signal is unobservable.

17. A computer program product for use in manufacturing circuits, the computer program product comprising:
a computer readable storage medium readable by a processing circuit and storing instructions for performing a method comprising:
detecting an unobservable cycle for at least one latch in a circuit design, wherein the unobservable cycle indicates that the at least one latch is not observable to downstream logic in the circuit design;
generating a coverage event to identify the unobservable cycle for the at least one latch;
tracking the coverage event to detect a state associated with the unobservable cycle and a state change cycle, wherein the state change cycle is determined based on a simulation technique, and wherein the state change cycle comprises a cycle in which the at least one latch changes values from a previous state;
determining a redundant switching of the at least one latch based on the state associated with the unobservable cycle and the state change cycle; and
initiating manufacturing of a circuit based on the circuit design, wherein the circuit design is modified to prevent the redundant switching of the at least one latch based in part on the unobservable cycle.

18. The computer program product of claim 17 , wherein the method further comprises generating an auxiliary latch associated with the at least one latch, wherein the auxiliary latch stores a previous value of the at least one latch.

19. The computer program product of claim 17 , wherein the unobservable cycle is based on a set of fanout points associated with the at least one latch.

20. The computer program product of claim 17 , wherein the detecting comprises detecting the unobservable cycle based on a set of sequential signals from interconnected computation logic.

Assignees

• IBM

Inventors

• Biran Giora
• Arbel Eli

Classifications

• G06F30/30 Primary

  Circuit design · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F11/3608

  using formal methods, e.g. model checking, abstract interpretation (theorem proving G06N5/013) · CPC title

• G06F30/3323

  using formal methods, e.g. equivalence checking or property checking · CPC title

• G06F30/3308 Primary

  using simulation · CPC title