Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation

Patent metadata

Field	Value
Publication number	US-10740126-B2
Application number	US-201816166010-A
Country	US
Kind code	B2
Filing date	Oct 19, 2018
Priority date	Mar 15, 2013
Publication date	Aug 11, 2020
Grant date	Aug 11, 2020

Abstract

Methods for supporting wide and efficient front-end operation with guest architecture emulation are disclosed. As a part of a method for supporting wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a cache line that includes the first far taken branch instruction, a next cache line and a cache line located at the target of the first far taken branch instruction is read. Based on information that is accessed from a data table, the cache line and either the next cache line or the cache line located at the target is fetched in a single cycle.

First claim

What is claimed is:

1. A processor, comprising:
a cache system, comprising:
a cache controller to:
fetch, a first cache line that includes a branch instruction and, based on information in a data table, either a second cache line that is adjacent to the first cache line in the instruction cache or a target cache line that is stored at a target address of the branch instruction,
wherein the information is populated in the data table upon moving the first cache line from an L2 cache to an L1 cache,
wherein the cache controller is to copy the target cache line to a shadow cache and the target cache line is fetched from the shadow cache, and
wherein the shadow cache has a same number of sets and half a number of ways as the instruction cache.

2. The processor of claim 1 , wherein the information in the data table is separate from the first cache line, including an indication of the target address in the cache line.

3. The processor of claim 1 , wherein the target cache line is stored in a same index of the shadow cache as is the first cache line in the instruction cache.

4. The processor of claim 1 , wherein the controller is to determine an offset of a target instruction in the target cache line relative to the branch instruction, compute a guest target based on said offset of said target instruction and a guest instruction pointer, and determine whether said guest target and a cached native target are valid based on a reference to a conversion-lookaside-buffer.

5. The processor of claim 1 , wherein the controller to select a predicted guest target from a guest target cache that stores guest targets and determine whether the predicted guest target is valid based on a reference to a conversion-lookaside-buffer.

6. The processor of claim 1 , wherein the information includes one or more of a branch instruction address of the branch instruction, an offset associated with the target cache line, a direct/indirect branch instruction identifier, and a native/guest branch instruction identifier.

7. A cache system, comprising:
a cache controller to:
fetch, a first cache line that includes a branch instruction and, based on information in a data table, either a second cache line that is adjacent to the first cache line in the instruction cache or a target cache line that is stored at a target address of the branch instruction,
wherein the information is populated in the data table upon moving the first cache line from an L2 cache to an L1 cache,
wherein the cache controller is to copy the target cache line to a shadow cache and the target cache line is fetched from the shadow cache, and
wherein the shadow cache has a same number of sets and half a number of ways as the instruction cache.

8. The cache system of claim 7 , wherein the information in the data table is separate from the first cache line, including an indication of the target address in the cache line.

9. The cache system of claim 7 , wherein the target cache line is stored in a same index of the shadow cache as is the first cache line in the instruction cache.

10. The cache system of claim 7 , wherein the controller is to determine an offset of a target instruction in the target cache line relative to the branch instruction, compute a guest target based on said offset of said target instruction and a guest instruction pointer, and determine whether said guest target and a cached native target are valid based on a reference to a conversion-lookaside-buffer.

11. The cache system of claim 7 , wherein the controller to select a predicted guest target from a guest target cache that stores guest targets and determine whether the predicted guest target is valid based on a reference to a conversion-lookaside-buffer.

12. The cache system of claim 7 , wherein the information includes one or more of a branch instruction address of the branch instruction, an offset associated with the target cache line, a direct/indirect branch instruction identifier, and a native/guest branch instruction identifier.

13. A non-transitory machine-readable storage medium that stores instructions, which when executed by a processor, causes the processor to:
fetch, a first cache line that includes a branch instruction and, based on information in a data table, either a second cache line that is adjacent to the first cache line in an instruction cache or a target cache line that is stored at a target address of the branch instruction, wherein the information is populated in the data table upon moving the first cache line from an L2 cache to an L1 cache, and
copy the target cache line to a shadow cache and the target cache line is fetched from the shadow cache,
wherein the shadow cache has a same number of sets and half a number of ways as the instruction cache.

14. The non-transitory machine-readable storage medium of claim 13 , wherein the information in the data table is separate from the first cache line, including an indication of the target address in the cache line.

15. The non-transitory machine-readable storage medium of claim 13 , wherein the target cache line is stored in a same index of the shadow cache as is the first cache line in the instruction cache.

16. The non-transitory machine-readable storage medium of claim 13 , wherein the controller is to determine an offset of a target instruction in the target cache line relative to the branch instruction, compute a guest target based on said offset of said target instruction and a guest instruction pointer, and determine whether said guest target and a cached native target are valid based on a reference to a conversion-lookaside-buffer.

17. The non-transitory machine-readable storage medium of claim 13 , wherein the information includes one or more of a branch instruction address of the branch instruction, an offset associated with the target cache line, a direct/indirect branch instruction identifier, and a native/guest branch instruction identifier.

Assignees

• Intel Corp

Inventors

• Abdallah Mohammad
• Groen Ankur
• Gunadi Erika
• Singh Mandeep
• Rao Ravishankar

Classifications

• G06F12/0875 Primary

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F9/323

  for indirect branch instructions · CPC title

• G06F9/30058

  Conditional branch instructions · CPC title

• G06F9/30065

  Loop control instructions; iterative instructions, e.g. LOOP, REPEAT · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title