Re-encoding data associated with failed memory devices

Patent metadata

Field	Value
Publication number	US-10735030-B2
Application number	US-201715670802-A
Country	US
Kind code	B2
Filing date	Aug 7, 2017
Priority date	Aug 7, 2017
Publication date	Aug 4, 2020
Grant date	Aug 4, 2020

Abstract

A technique includes determining that a given memory device of a plurality of memory devices has failed and in response to the determination that the given memory device has failed, re-encoding a data unit associated with the given memory device. The data unit is associated with a payload and a symbol-based error correction code. The re-encoding includes determining a bit-based error correction code for the payload and replacing the data unit in the memory with the payload and the bit-based error correction code.

First claim

What is claimed is:

1. A method comprising:
determining that a given memory device of a plurality of memory devices has failed; and
in response to the determination of the failed memory device and further in response to identifying a plurality of wear-leveling memory regions associated with the failed memory device:
reading a first data unit from a respective wear-leveling memory region associated with the failed memory device, the first data unit including a first payload and a symbol-based error correction code;
correcting an error in the first payload based on the symbol-based error correction code to produce a corrected payload;
re-encoding the first data unit associated with the failed memory device to a second data unit by determining a bit-based error correction code for the corrected payload; and
storing the second data unit, the second data unit having a format such that that the second data unit is stored in at least one of the plurality of memory devices but is not stored in the failed memory device.

2. The method of claim 1 , further comprising determining that the given memory device has failed based on at least one of the following:
a number of observed errors associated with the given memory device, a region of the memory associated with the given memory device, or an error rate associated with the given memory device.

3. The method of claim 1 , wherein the bit-based error correction code comprises Bose Chaudhuri Hocquenghem (BCH)-based error correction code.

4. The method of claim 1 , wherein the symbol-based error correction code comprises Reed Solomon-based error correction code.

5. The method of claim 1 , further comprising erasing the failed memory device.

6. An apparatus comprising:
a memory including a plurality of memory devices; and
a memory controller to:
determine that a given memory device of the plurality of memory devices has failed; and
in response to the determination of the failed memory device and further in response to identifying a plurality of wear-leveling memory regions associated with the failed memory device:
read a first data unit from a respective wear-leveling memory region associated with the failed memory device, wherein the first data unit comprises a first payload and a symbol-based error correction code;
correct an error in the first payload based on the symbol-based error correction code to produce a corrected payload;
re-encode the read first data unit to a second data unit by determining a bit-based error correction code for the corrected payload; and
write the second data unit to the memory, the second data unit having a format such that the second data unit is written to at least one of the plurality of memory devices but is not written to the failed memory device.

7. The apparatus of claim 6 , wherein the memory controller comprises:
a decoder to selectively correct the error in the first payload of the read first data unit based on the symbol-based error correction code.

8. The apparatus of claim 7 , wherein the memory controller comprises:
an encoder to generate the bit-based error correction code based on the selectively corrected error in the first payload.

9. The apparatus of claim 6 , wherein the memory controller updates metadata associated with the read first data unit to represent bit-based error correction code encoding for the second data unit.

10. The apparatus of claim 6 , wherein the memory comprises a non-volatile memory.

11. The apparatus of claim 6 , wherein the symbol-based error correction code comprises Reed Solomon error correction code.

12. The apparatus of claim 6 , wherein the bit-based error correction code comprises Bose Chaudhuri Hocquenghem (BCH).

13. The apparatus of claim 6 , wherein the symbol-based error correction code is associated with a larger size than a size of the bit-based error correction code.

14. The apparatus of claim 6 , wherein a first subset of the plurality of memory devices is associated with the symbol-based error correction code and a second subset of the plurality of memory devices is associated with the bit-based error correction code.

15. The apparatus of claim 6 , wherein the memory controller erases the failed memory device of the memory from which the first data unit is read.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Lesartre Gregg B
• Ray Harvey
• Miller Kevin L
• Brueggen Chris Michael
• Foltin Martin

Classifications

• H03M13/152 Primary

  Bose-Chaudhuri-Hocquenghem [BCH] codes · CPC title

• H03M13/353

  Adaptation to the channel · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• H03M13/1515

  Reed-Solomon codes · CPC title

• H03M13/3776 Primary

  using a re-encoding step during the decoding process · CPC title