Multi-rate DEM with mismatch noise cancellation for digitally-controlled oscillators

Patent metadata

Field	Value
Publication number	US-10735005-B2
Application number	US-201916546717-A
Country	US
Kind code	B2
Filing date	Aug 21, 2019
Priority date	Aug 24, 2018
Publication date	Aug 4, 2020
Grant date	Aug 4, 2020

Abstract

A digital fractional-N phase locked loop (PLL) with multi-rate dynamic element matching (DEM) and an adaptive mismatch-noise cancellation (MNC) is provided. The PLL includes a phase error to digital converter and a digital loop filter to suppress quantization noise of the phase error to digital converter and drive a digitally controlled oscillator. A digitally controlled oscillator (DCO) with a multi-rate DEM encoder includes an integer bank of frequency control elements (FCE) and a fractional bank of frequency control elements. Adaptive mismatch-noise cancellation logic operates to cancel DCO phase error arising from frequency control element (FCE) static and dynamic mismatch error by estimating ideal MNC coefficient values during PLL normal operation, estimating MNC coefficient errors at each sample time, and updating the MNC coefficient values to approach zero (FCE) static and dynamic mismatch error.

First claim

The invention claimed is:

1. A digital fractional-N phase locked loop (PLL) with multi-rate dynamic element matching (DEM) and an adaptive mismatch-noise cancellation (MNC), comprising:
a phase error to digital converter;
a digital loop filter to suppress quantization noise of the phase error to digital converter and drive a digitally controlled oscillator;
a digitally controlled oscillator (DCO) with a multi-rate DEM encoder driving an integer bank of frequency control elements and a fractional bank of frequency control elements; and
adaptive mismatch-noise cancellation logic operating to cancel DCO phase error arising from frequency control element (FCE) static and dynamic mismatch error by estimating ideal MNC coefficient values during PLL normal operation, estimating MNC coefficient errors at each sample time, and updating the MNC coefficient values to approach zero FCE static and dynamic mismatch error.

2. The digital fractional-N phase locked loop of claim 1 , wherein the updating of the MNC coefficient values is conducted once for each time the phase error of the PLL is measured.

3. The digital fractional-N phase locked loop of claim 1 , wherein the multi-rate DEM comprises:
a slow DEM encoder that drives the integer bank of frequency control elements and a second order ΔΣ modulator; and a fractional path, wherein the fractional path includes the second-order digital ΔΣ modulator driving a fast DEM encoder that drives the fractional bank of frequency control elements, wherein the second-order digital ΔΣ modulator and fast DEM encoder are clocked at a higher frequency compared to that of the slow DEM encoder.

4. The digital fractional-N phase locked loop of claim 3 , wherein the ΔΣ modulator's quantization noise is asymptotically independent of its input and dither sequences used in the ΔΣ modulator.

5. The digital fractional-N phase locked loop of claim 3 , wherein the adaptive mismatch-noise cancellation logic injects an MNC correction sequence, which is computed from the MNC coefficient values and the switching sequences generated inside the slow DEM encoder, into the fractional path.

6. The digital fractional-N phase locked loop of claim 3 , wherein the adaptive mismatch-noise cancellation logic estimates the ideal MNC coefficients with a least-mean-square (LMS)-like algorithm.

7. The digital fractional-N phase locked loop of claim 3 , wherein the adaptive mismatch-noise cancellation logic estimates the ideal MNC coefficients based on the statistical properties of switching sequences generated inside the slow DEM encoder.

Assignees

• Univ California

Inventors

• Galton Ian
• Alvarez-Fontecilla Enrique

Classifications

• H03M3/50

  Digital/analogue converters using delta-sigma modulation as an intermediate step (digital delta-sigma modulators per se H03M7/3004) · CPC title

• H03L7/0991

  the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814) · CPC title

• H03L7/1974

  for fractional frequency division · CPC title

• H03L7/193

  the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider · CPC title

• H03L7/093 Primary

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title