Method and system for providing regional electrical grid for power conservation in a programmable device

Patent metadata

Field	Value
Publication number	US-10735002-B2
Application number	US-201916730716-A
Country	US
Kind code	B2
Filing date	Dec 30, 2019
Priority date	Nov 7, 2018
Publication date	Aug 4, 2020
Grant date	Aug 4, 2020

Abstract

A programmable semiconductor device capable of being selectively programmed to perform one or more logic functions includes a first region, second region, first regional power control (“RPC”), and second-to-first power control connection. The first region, in one embodiment, contains first configurable logic blocks (“CLBs”) able to be selectively programmed to perform a first logic function. The second region includes a group of second CLBs configured to be selectively programmed to perform a second logic function. The first RPC port or inter-chip port which is coupled between the first and second regions facilitates dynamic power supply to the first region in response to the data in the second region. The second-to-first power control connection is used to allow the second region to facilitate and/or control power to the first region.

First claim

What is claimed is:

1. A programmable integrated circuit (“IC”) able to be selectively programmed to perform one or more logic functions, comprising:
a first region of the programmable IC able to be selectively programmed to perform a first logic function, and the first region operable under a first dynamic power region (“DPR”) for power supply;
a second region of the programmable IC, configured to be selectively programmed to perform a second logic function, situated adjacent to the first region of the programmable IC and operable under a second DPR for power supply;
a first logic element situated within the second region of the programmable IC and configured to provide a first regional power control signal to control power supply to the first DPR; and
a second logic element situated in a third region of the programmable IC and configured to provide a second regional power control signal to control power supply to the second DPR.

2. The programmable IC of claim 1 , further comprising a first regional power control (“RPC”) port coupled to the first region and configured to dynamically control power supply to the first region.

3. The programmable IC of claim 2 , further comprising a second-to-first power control connection, coupling between the second region and the first RPC port, configured to allow the second region to control power supply to the first region.

4. The programmable IC of claim 1 , further comprising a second RPC port coupled to the second region and configured to dynamically control power supply to the second region.

5. The programmable IC of claim 4 , further comprising a first-to-second power control connection coupling between the first region and the second RPC port and configured to allow the first region to selectively control power supply to the second region.

6. The programmable IC of claim 1 , further comprising a first configuration memory coupled to the first region and figured to store first configuration for the first region.

7. The programmable IC of claim 1 , further comprising a second configuration memory coupled to the second region and figured to store second configuration for the second region.

8. The programmable IC of claim 1 , wherein the first region is configured to switch into a sleep mode when the first RPC port provides substantially no power.

9. The programmable IC of claim 1 , further comprising a third-to-first power control connection, coupling between the third region and the first RPC port, configured to allow the third region to control power supply to the first region.

10. A field programmable gate array (“FPGA”) containing configurable logic blocks, configuration memory, and routing fabric and able to be selectively programmed to perform one or more logic functions, the FPGA comprising:
a plurality of dynamic power regions (“DPRs”) partitioning from the FPGA operable under a power grid containing a plurality of regional dynamic power supplies, each of the plurality of DPRs assigned to one of the plurality of regional dynamic power supplies;
one or more logic elements coupled to the plurality of DPRs and configured to provide regional power control signals for controlling power supplies to one or more plurality of DPRs; and
one or more primitives coupled to the one or more logic elements for facilitating each of the one or more DPRs to have an independent power supply from neighboring DPRs in response to the regional power control signals.

11. The FPGA of claim 10 , wherein the plurality of DPRs are mapped into a plurality of physical power regions (“PPRs”) of the FPGA for implementing power conservation.

12. The FPGA of claim 11 , further comprising a plurality of region power control (“RPC”) ports coupled to the one or more primitives for allowing each of the plurality of PPRs to independently provide a power supply to a neighboring PPR in response to a result processed based on input data received at each PPR.

13. The FPGA of claim 12 , wherein the plurality of RPC ports are dedicated physical ports for facilitating power supply to various PPRs.

14. The FPGA of claim 12 , wherein each of the plurality of RPC ports is being controlled by at least one of the PPRs.

15. The FPGA of claim 10 , further comprising a power distribution fabric (“PDF”) coupled to the plurality of DPRs and configured to facilitate internal power supply.

16. The FPGA of claim 10 , further a programmable interconnection array (“PIA”) coupled to the plurality of the DPRs for facilitating dynamic runtime power supply.

17. The FPGA of claim 16 , wherein the PIA includes a power distribution fabric for power distribution.

18. A method of a programmable semiconductor device (“PLD”) partitioned into multiple dynamic power regions (“DPRs”) facilitating dynamically power-down and power-up a portion of the PLD for power conservation, the method comprising:
generating a first power control signal by a logic residing in a second DPR in accordance with a first result of data processing by a portion of second configurable logic blocks (“LBs”);
waking up at least a portion of a plurality of first configurable LBs of a first DPR in response to the first power control signal received by a first regional power control (“RPC”) port from the second DPR;
generating a third power control signal by the first DPR in response to a third result processed by at least a portion of first configurable LBs after the first DPR resumes operation; and
waking up at least a portion of a plurality of third configurable LBs of a third DPR in response to the third power control signal received by a third regional power control (“RPC”) port from the first DPR.

19. The method of claim 18 , further comprising forwarding the first power control signal from the second region to a first RPC port via a second-to-first power connection coupling the second region to the first region.

20. The method of claim 18 , further comprising maintaining power supply to the first memory while the first DPR is phased into sleeping mode for power consumption.

21. The method of claim 18 , further comprising terminating the first power control signal by the second DPR according to a second result from data processing by at least a portion of the plurality of second configurable LBs.

22. The method of claim 19 , further comprising powering down the first DPR when the first RPC port stops receiving the first power control signal.

Assignees

• Zhu Jinghui
• Liu Jianhua
• Song Ning
• Gowin Semiconductor Corp

Inventors

• Zhu Jinghui
• Liu Jianhua
• Song Ning

Classifications

• H03K19/17784 Primary

  for supply voltage · CPC title

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• H03K19/17724 Primary

  Structural details of logic blocks · CPC title

• G06F13/1673 Primary

  using buffers · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title