Driving circuit for power switch

Patent metadata

Field	Value
Publication number	US-10734976-B2
Application number	US-201916548781-A
Country	US
Kind code	B2
Filing date	Aug 22, 2019
Priority date	Dec 1, 2015
Publication date	Aug 4, 2020
Grant date	Aug 4, 2020

Abstract

A driving circuit for driving a power switch. The driving circuit and the power switch are collaboratively defined as an equivalent circuit. The equivalent circuit includes a first equivalent capacitor corresponding to an input capacitor of the power switch, an equivalent inductor, and a second equivalent capacitor corresponding to a parasitic parameter of at least one driving switch. In the charging procedure or the discharging of the first equivalent capacitor, a change amount of charges in the first equivalent capacitor while a voltage of the input capacitor is changed from a voltage corresponding to no inductor current to a set voltage is larger than or equal to a change amount of charges in the second equivalent capacitor while the voltage of the input capacitor is changed from the voltage corresponding to no inductor current to a steady voltage.

First claim

What is claimed is:

1. A driving circuit for driving a power switch comprising an input capacitor, the driving circuit comprising:
an inductor;
a resistor comprising a parasitic resistor of the driving circuit; and
a first driving switch and a second driving switch electrically connected with the inductor, wherein the first driving switch and the second driving switch are electrically connected with each other and electrically connected with the inductor, wherein the first driving switch comprises a first parasitic capacitor and the second driving switch comprises a second parasitic capacitor,
wherein the driving circuit is configured such that a first equivalent capacitor is formed corresponding to the input capacitor, and a second equivalent capacitor is formed corresponding to one or both of the first and second parasitic capacitors,
wherein the first equivalent capacitor, the inductor, the resistor and the second equivalent capacitor are serially connected with each other to form an equivalent circuit to charge the input capacitor of the power switch, and a charging procedure of the input capacitor is performed through the equivalent circuit,
wherein during the charging procedure, firstly, the first driving switch and the second driving switch are turned on by turns, which causes a voltage of the input capacitor to increase to a maximum voltage Vp 1 , and there is substantially no inductor current when the voltage of the input capacitor is at the maximum voltage Vp 1 , then, the first driving switch and the second driving switch are turned off, which causes the voltage of the input capacitor to decrease from the maximum voltage to a first steady voltage,
wherein the first and second equivalent capacitors are configured such that:
(1) during the charging procedure, while the voltage of the input capacitor is changed from the maximum voltage Vp 1 to the first steady voltage, a first amount of charges discharged from the input capacitor is equal to Q 1 , whereas while the voltage of the input capacitor is changed from the maximum voltage Vp 1 to a first set voltage VH, a second amount of charges discharged from the input capacitor is equal to Q 2 , wherein Q 2 is greater than or equal to Q 1 , and
(2) the first steady voltage is higher than the first set voltage VH, and the first set voltage VH is higher than a maximum threshold Vmax of a gate terminal of the power switch.

2. The driving circuit according to claim 1 , wherein a first terminal of the first driving switch is electrically connected with an input power source, a second terminal of the first driving switch is electrically connected with a first terminal of the second driving switch and a first terminal of the inductor, a second terminal of the second driving switch is connected with a ground terminal, a second terminal of the inductor is electrically connected with a first terminal of the resistor, and a second terminal of the resistor is electrically connected with the input capacitor.

3. The driving circuit according to claim 2 , wherein the first equivalent capacitor is formed corresponding to the input capacitor and the second equivalent capacitor is formed corresponding to the first parasitic capacitor and the second parasitic capacitor, such that:
Q 1=Coss31× Vo 1 +Coss32× Vo 1

Q 2=Ciss×( Vp 1 −VH )

where Coss 31 is a capacitance of the first parasitic capacitor, Coss 32 is a capacitance of the second parasitic capacitor, Ciss is a capacitance of the input capacitor, Vo 1 is the first steady voltage, and Vcc is a voltage of the input power source.

4. The driving circuit according to claim 2 , wherein the driving circuit further comprises a first clamping circuit and a second clamping circuit, the first clamping circuit comprises a third parasitic capacitor, and the second clamping circuit comprises a fourth parasitic capacitor, wherein a first terminal of the first clamping circuit is connected with the first terminal of the first driving switch and the input power source, a second terminal of the first clamping circuit is connected with the second terminal of the inductor, a first terminal of the second clamping circuit and the first terminal of the resistor, and a second terminal of the second clamping circuit is connected with the ground terminal, wherein when the voltage of the input capacitor is higher than an over-voltage value, the voltage of the input capacitor is clamped to the over-voltage value by the first clamping circuit, wherein when the voltage of the input capacitor is lower than an under-voltage value, the voltage of the input capacitor is clamped to the under-voltage value by the second clamping circuit.

5. The driving circuit according to claim 4 , wherein the first equivalent capacitor is formed corresponding to the input capacitor, the third parasitic capacitor and the fourth parasitic capacitor, the second equivalent capacitor is formed corresponding to the first parasitic capacitor and the second parasitic capacitor, such that:
Q 1=(Coss31+Coss32)× Vo 1

Q 2=(Ciss+Coss34+Coss35)×( Vp 1 −VH )

where Coss 31 is a capacitance of the first parasitic capacitor, Coss 32 is a capacitance of the second parasitic capacitor, Ciss is a capacitance of the input capacitor, Coss 35 is a capacitance of the third parasitic capacitor of the first clamping circuit, Vo 1 is the first steady voltage, and Coss 34 is a capacitance of the fourth parasitic capacitor of the second clamping circuit.

6. The driving circuit according to claim 2 , wherein the driving circuit further comprises a third driving switch, and the third driving switch has a third parasitic capacitor, wherein a first terminal of the third driving switch is electrically connected with the second terminal of the inductor and the first terminal of the resistor, a second terminal of the third driving switch is electrically connected with the ground terminal, wherein the driving circuit turns on the third driving switch to discharge the input capacitor.

7. The driving circuit according to claim 6 , wherein the first equivalent capacitor is formed corresponding to the input capacitor and the third parasitic capacitor, the second equivalent capacitor is formed corresponding to the first parasitic capacitor and the second parasitic capacitor, such that:
Q 1=(Coss31+Coss32)× Vo 1

Q 2=(Ciss+Coss33)×( Vp 1 −VH )

where Coss 31 is a capacitance of the first parasitic capacitor, Coss 32 is a capacitance of the second parasitic capacitor, Ciss is a capacitance of the input capacitor, Vo 1 is the first steady voltage, and Coss 33 is a capacitance of the third parasitic capacitor.

8. The driving circuit according to claim 6 , wherein the driving circuit further comprises a first clamping circuit having a fourth parasitic capacitor, wherein a first terminal of the first clamping circuit is connected with the first terminal of the first driving switch and the input power source, a second terminal of the first clamping circuit is connected with the second terminal of the inductor, and a first terminal of the third driving switch and the first terminal of the resistor, wherein when the voltage of the input capacitor is higher than an over-voltage value, the voltage of the input capacitor is clamped to the over-voltage value by the first clamping circuit.

9. The driving circuit according to claim 8 , wherein the first equivalent capacitor is formed corresponding to the input capacitor, the third parasitic capacitor and the fourth parasitic capacitor, the second equivalent capacitor is formed corresponding to the first parasitic capacitor and the second parasitic capacitor, such that:
Q 1=(Coss31+Coss32)× Vo 1

Q 2=(Ciss+Coss33+Cos

Assignees

• Delta Electronics Inc

Inventors

• Hu Peiqing
• Zeng Jianhong
• Ye Haoyi

Classifications

• H02M1/08 Primary

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M1/346

  Passive non-dissipative snubbers · CPC title

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title

• H03K3/012 Primary

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H03K17/163

  Soft switching · CPC title