Die stack assembly using an edge separation structure for connectivity through a die of the stack

Patent metadata

Field	Value
Publication number	US-10734362-B2
Application number	US-201715619516-A
Country	US
Kind code	B2
Filing date	Jun 11, 2017
Priority date	Feb 29, 2016
Publication date	Aug 4, 2020
Grant date	Aug 4, 2020

Abstract

A die stack assembly includes first and second power semiconductor device dice. The first die has a P type peripheral edge separation structure that extends from the top planar semiconductor surface of the first die all the way to the bottom planar semiconductor surface of the die, and that is doped at least in part with aluminum. The backside of the first die is mounted to the backside of the second die. A metal feature that is not covered with passivation, and that can serve as a bonding pad, is disposed on part of the peripheral edge separation structure. A metal member (for example, a bond wire or metal clip) contacts the metal feature such that an electrical connection is established from the metal member, through the metal feature, through the peripheral edge separation structure of the first die, and to an electrode of the second die.

First claim

What is claimed is:

1. A method comprising:
(a) wafer bonding a backside of a first wafer to a backside of a second wafer thereby obtaining a bonded wafer structure;
(b) dicing the bonded wafer structure thereby obtaining a power semiconductor device die assembly, wherein the power semiconductor device die assembly comprises a first power semiconductor device die and a second power semiconductor device die, wherein the first power semiconductor device die comprises a peripheral edge separation structure that extends from a first substantially planar semiconductor surface of the first power semiconductor device die to a second substantially planar semiconductor surface of the first power semiconductor device die along a side edge of the first power semiconductor device die, wherein the second power semiconductor device die comprises a peripheral edge separation structure that extends from a first substantially planar semiconductor surface of the second power semiconductor device die to a second substantially planar semiconductor surface of the second power semiconductor device die along a side edge of the second power semiconductor device die;
(c) forming an anode of the power semiconductor device die assembly by providing a metal feature that covers and makes electrical contact with the peripheral edge separation structure at the first substantially planar semiconductor surface of the first power semiconductor device die, wherein the metal feature is electrically coupled within the assembly through the peripheral edge separation structure of the first power semiconductor device die to the peripheral edge separation structure of the second power semiconductor device die; and
forming a cathode of the power semiconductor device die assembly by providing a further metal feature that covers and makes electrical contact with a region of the first substantially planar semiconductor surface,
wherein the second power semiconductor device die forms an anode gated thyristor, wherein a metal contact structure is not formed on the peripheral edge separation structure of the second power semiconductor device die.

2. The method of claim 1 , further comprising:
(c) attaching a bond wire to a bond pad, wherein the bond pad is disposed on a surface area of the peripheral edge separation structure of the first power semiconductor device die.

3. The method of claim 1 , further comprising:
(c) attaching a wafer interface member to a topside of the second wafer prior to the dicing of (b) such that when the dicing of (b) occurs the wafer interface member is diced along with the first and second wafers, wherein the power semiconductor device die assembly comprises the first power semiconductor device die, the second power semiconductor device die, and a die-sized interface member cut from the wafer interface member, wherein the die-sized interface member comprises a first metal feature and a second metal feature, wherein the first metal feature is in electrical contact with a first metal electrode of the second power semiconductor device die, and wherein the second metal feature is in electrical contact with a second metal electrode of the second power semiconductor device die.

4. The method of claim 1 , wherein the peripheral edge separation structure of the first power semiconductor device die is a region of P type semiconductor material, and wherein no part of the side edge of the first power semiconductor device die is N type semiconductor material.

5. The method of claim 1 , wherein the first power semiconductor device die has a control electrode disposed on the first substantially planar semiconductor surface of the first power semiconductor device die, and wherein the second power semiconductor device die has a control electrode disposed on the first substantially planar semiconductor surface of the second power semiconductor device die.

6. The method of claim 5 , wherein the peripheral edge separation structure of the first die is a region of P type semiconductor material, and wherein no part of the side edge of the first die is N type semiconductor material.

7. The method of claim 5 , wherein the first die has a control electrode disposed on the first substantially planar semiconductor surface of the first die, and wherein the second die has a control electrode disposed on the first substantially planar semiconductor surface of the second die.

8. The method of claim 1 , wherein the first power semiconductor device die further comprises a metal layer disposed on the second substantially planar semiconductor surface of the first power semiconductor device die, wherein the second power semiconductor device die further comprises a metal layer disposed on the second substantially planar semiconductor surface of the second power semiconductor device die, and wherein the metal layer of the first power semiconductor device die is bonded to the metal layer of the second power semiconductor device die.

9. The method of claim 8 , wherein a layer comprising silver bonds the metal layer disposed on the second substantially planar semiconductor surface of the first power semiconductor device die to the metal layer disposed on the second substantially planar semiconductor surface of the second power semiconductor device die.

10. The method of claim 9 , wherein the wafer bonding of (a) involves sintering the layer comprising silver.

11. A method comprising:
wafer bonding a backside of a first wafer to a backside of a second wafer thereby obtaining a bonded wafer structure;
dicing the bonded wafer structure to obtain a die assembly, wherein the die assembly comprises a first die and a second die, wherein the first die comprises a peripheral edge separation structure that extends from a first substantially planar semiconductor surface of the first die to a second substantially planar semiconductor surface of the first die along a side edge of the first die, wherein the second die comprises a peripheral edge separation structure that extends from a first substantially planar semiconductor surface of the second die to a second substantially planar semiconductor surface of the second die along a side edge of the second die, wherein the peripheral edge separation structure of the first die is a region of P type semiconductor material;
forming an anode of the power semiconductor device die assembly by providing an amount of metal that covers and makes electrical contact with the peripheral edge separation structure at the first substantially planar semiconductor surface of the first die, and wherein the amount of metal is electrically coupled within the assembly through the peripheral edge separation structure of the first die to the peripheral edge separation structure of the second die; and
forming a cathode of the power semiconductor device die assembly by providing a further metal feature that covers and makes electrical contact with a region of the first substantially planar semiconductor surface, wherein the second die forms an anode gated thyristor, wherein a metal contact structure is not formed on the peripheral edge separation structure of the second die.

12. The method of claim 11 , further comprising:
attaching a bond wire to a bond pad, wherein the bond pad is disposed on a surface area of the peripheral edge separation structure of the first die.

13. The method of claim 11 , further comprising:
attaching a wafer interface member to a topside of the second wafer prior to the dicing such that the wafer interface member is diced along with the first and second wafers, wherein the die assembly comprises the first die, the second die, and a die-sized interface member cut from the wafer i

Assignees

• Littelfuse Inc

Inventors

• Wisotzki Elmar
• Ettingshausen Frank

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/764

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title