Printed circuit board

Patent metadata

Field	Value
Publication number	US-10734248-B2
Application number	US-201916662583-A
Country	US
Kind code	B2
Filing date	Oct 24, 2019
Priority date	Sep 29, 2017
Publication date	Aug 4, 2020
Grant date	Aug 4, 2020

Abstract

A printed circuit board according to an embodiment includes: an insulating layer; a first pad disposed on a first surface of the insulating layer; a first conductive layer disposed on the first pad and including gold (Au); a second pad disposed on a second surface of the insulating layer; and a second conductive layer disposed on the second pad and including gold (Au), wherein the first conductive layer is a conductive layer connected to a wire, the second conductive layer is a conductive layer connected to a solder, and the first conductive layer is thicker than the second conductive layer.

First claim

The invention claimed is:

1. A printed circuit board comprising:
an insulating layer;
a first pad disposed on a first surface of the insulating layer;
a first conductive layer disposed on the first pad and including gold (Au);
a second pad disposed on a second surface of the insulating layer; and
a second conductive layer disposed on the second pad and including gold (Au),
wherein the first conductive layer includes a first region in contact with the first pad and a second region spaced apart from the first pad,
wherein the first region of the first conductive layer and the second region of the first conductive layer are monolithically formed with each other,
wherein the second region of the first conductive layer comprises a portion of the first conductive layer that is closest to the insulating layer and is spaced apart from the first pad,
wherein the second conductive layer includes a first region in contact with the second pad and a second region spaced apart from the second pad,
wherein the first region of the second conductive layer and the second region of the second conductive layer are monolithically formed with each other,
wherein the second region of the second conductive layer comprises a portion of the second conductive layer that is closest to the insulating layer and is spaced apart from the second pad, and
wherein the first conductive layer is thicker than the second conductive layer.

2. The printed circuit board of claim 1 , wherein the first conductive layer is connected to a wire, and wherein the second conductive layer is connected to a solder.

3. The printed circuit board of claim 1 , wherein the insulating layer includes a plurality of insulating layers,
wherein the first pad is disposed on an upper surface of a first insulating layer disposed at an uppermost portion of the plurality of insulating layers, and
wherein the second pad is disposed under a lower surface of a second insulating layer disposed at a lowermost portion of the plurality of insulating layers.

4. The printed circuit board of claim 1 , wherein the first pad has a narrower width than the second pad.

5. The printed circuit board of claim 1 , wherein the first conductive layer and the second conductive layer are formed by electrolytic plating.

6. The printed circuit board of claim 3 , wherein each of the first pad and the second pad includes:
a plating seed layer disposed at a surface of the uppermost insulating layer or the lowermost insulating layer and including copper;
a first pattern disposed on the plating seed layer and including copper; and
a second pattern disposed on the first pattern and including copper.

7. The printed circuit board of claim 6 , wherein the first pattern of the first pad is thicker than the second pattern of the first pad, and
wherein the first pattern of the second pad is thicker than the second pattern of the second pad.

8. The printed circuit board of claim 6 , wherein a central portion of an upper surface of the first pattern of the first pad is located higher than an outer side portion of the first pattern of the first pad, and
wherein a central portion of an upper surface of the first pattern of the second pad is located higher than an outer side portion of the first pattern of the second pad.

9. The printed circuit board of claim 6 , wherein a width of an upper surface of the first pattern of the first pad is larger than a width of a lower surface of the first pattern of the first pad, and
wherein a width of an upper surface of the first pattern of the second pad is larger than a width of a lower surface of the first pattern of the second pad.

10. The printed circuit board of claim 6 , wherein the first region of the first conductive layer is in direct physical contact with the second pattern of the first pad and the second region of the first conductive layer extends from the first region of the first conductive layer and is spaced apart from the plating seed layer of the first pad, the first pattern of the first pad, and the second pattern of the first pad, and
wherein the second region of the first conductive layer is not in physical contact with any of the plating seed layer of the first pad, the first pattern of the first pad, and the second pattern of the first pad.

11. The printed circuit board of claim 10 , wherein the first region of the second conductive layer is in direct physical contact with the second pattern of the second pad and the second region of the second conductive layer extends from the first region of the second conductive layer and is spaced apart from the plating seed layer of the second pad, the first pattern of the second pad, and the second pattern of the second pad, and
wherein the second region of the second conductive layer is not in physical contact with any of the plating seed layer of the second pad, the first pattern of the second pad, and the second pattern of the second pad.

12. A printed circuit board comprising:
an insulating layer;
a first pad disposed on a first surface of the insulating layer;
a second pad disposed on a second surface of the insulating layer opposite to the first surface; and
a first conductive layer disposed on the first pad,
wherein the first conductive layer includes:
a first region in direct physical contact with an upper surface of the first pad; and
a second region extending from the first region and spaced apart from the first pad,
wherein the first region of the first conductive layer and the second region of the first conductive layer are monolithically formed with each other,
wherein the second region of the first conductive layer comprises a portion of the first conductive layer that is closest to the insulating layer and is spaced apart from the first pad, and
wherein a width of an upper surface of the first pad is larger than that of a lower surface thereof.

13. The printed circuit board of claim 12 , wherein the first conductive layer includes a third region disposed between the first region and the second region, and in direct physical contact with a side surface of the first pad.

14. The printed circuit board of claim 12 , wherein the first conductive layer includes gold (Au),
wherein the printed circuit board includes a second conductive layer disposed on the second pad and including gold (Au), and
wherein the second conductive layer includes a first region in direct physical contact with a lower surface of the second pad and a second region extending from the first region and spaced apart from the second pad.

15. The printed circuit board of claim 14 , wherein a thickness, in a longitudinal direction perpendicular to the first surface of the insulating layer, of the first region of the first conductive layer is greater than a thickness, in the longitudinal direction, of the first region of the second conductive layer.

16. The printed circuit board of claim 12 , comprising an electronic component on the first surface of the insulating layer.

17. The printed circuit board of claim 14 , wherein each of the first pad and the second pad includes:
a plating seed layer disposed on the first surface or the second surface of the insulating layer and including copper;
a first pattern disposed on the plating seed layer and including copper; and
a second pattern disposed on the first pattern and including copper.

18. The printed circuit board of claim 17 , wherein an end portion of the second region of the first conductive layer is located higher than an outer side region of an upper surface of the first pattern of

Assignees

• Lg Innotek Co Ltd

Inventors

• Cho Sung Oh
• Kim Yoon Tai

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/701 Primary

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/66

  Conductive materials thereof · CPC title