GPU mixed primitive topology type processing

Patent metadata

Field	Value
Publication number	US-10733690-B2
Application number	US-201815982693-A
Country	US
Kind code	B2
Filing date	May 17, 2018
Priority date	May 17, 2018
Publication date	Aug 4, 2020
Grant date	Aug 4, 2020

Abstract

Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.

First claim

What is claimed is:

1. An apparatus comprising:
one or more processor cores; and
a memory to store data for graphics processing, wherein the one or more processor cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered, an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for a plurality of primitive topology types, and an indirection buffer for the index buffer, the indirection buffer to indicate topology type, index count, and offset value for the index buffer for each of the plurality of primitive topology types, wherein the index data for each primitive topology type of the plurality of primitive topology types is offset in the index buffer by the offset value indicated in the indirection buffer for the primitive topology type;
wherein the one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer according to the topology type, index count, and offset value for each plurality of primitive topology type provided in the indirection buffer and fetch vertex data from the vertex buffer; and
wherein the one or more processor cores are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.

2. The apparatus of claim 1 , wherein the index buffer is to further include index data for one or more non-indexed primitive topology types, the indirection buffer to include topology type, vertex count, and offset into the vertex buffer for each of the one or more non-indexed primitive topology types.

3. The apparatus of claim 1 , wherein the plurality of primitive topology types includes one or more of points, lines, triangles, and quads.

4. The apparatus of claim 1 , further comprising a geometry shader to support output of a plurality of primitive topology types in each of one or more output streams.

5. The apparatus of claim 4 , wherein the geometry shader is to filter primitive topology types and to convert one or more primitive topology types to one or more other primitive topology types.

6. The apparatus of claim 4 , wherein converting one or more primitive topology types to one or more other primitive topology types includes one or more of converting a small triangle to a point or converting two triangles into a quad.

7. A non-transitory computer-readable storage medium having stored thereon data representing sequences of instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
loading a mesh for computer graphics, the mesh including a plurality of primitive topology types;
generating a single vertex buffer in a computer memory for storage of vertex data for the mesh;
generating a single index buffer in the computer memory for storage of index data to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for each of the plurality of primitive topology types;
generating an indirection buffer for the index buffer, the indirection buffer to indicate topology type, index count, and offset value for the index buffer for each of the plurality of primitive topology types, wherein the index data for each primitive topology type of the plurality of primitive topology types is offset in the index buffer by the offset value indicated in the indirection buffer for the primitive topology type; and
executing a draw operation utilizing the index data for the plurality of primitive topology types from the index buffer according to the topology type, index count, and offset value for each plurality of primitive topology type provided in the indirection buffer, the draw operation including each of the plurality of primitive topology types.

8. The medium of claim 7 , wherein generating the index buffer in the computer memory further includes the index buffer being structured to include index data for one or more non-indexed primitive topology types, the indirection buffer to include topology type, vertex count, and offset into the vertex buffer for each of the one or more non-indexed primitive topology types.

9. The medium of claim 7 , further comprising instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising:
generating an output of a plurality of primitive topology types in each of one or more output streams.

10. The medium of claim 9 , further comprising instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising:
filtering primitive topology types; and
converting one or more primitive topology types to one or more other primitive topology types.

11. A processing system comprising:
one or more processor cores;
an input assembler;
a vertex fetch unit;
a rasterizer; and
memory to store data for graphics processing, wherein the one or more processor cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered, an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for a plurality of primitive topology types, and an indirection buffer for the index buffer, the indirection buffer to indicate topology type, index count, and offset value for the index buffer for each of the plurality of primitive topology types, wherein the index data for each primitive topology type of the plurality of primitive topology types is offset in the index buffer by the offset value indicated in the indirection buffer for the primitive topology type;
wherein the input assembler is to process the index data for the plurality of primitive topology types from the index buffer according to the topology type, index count, and offset value for each plurality of primitive topology type provided in the indirection buffer and to fetch vertex data from the vertex buffer; and
wherein the input assembler is to communicate a message to the rasterizer to set up each primitive topology type of the plurality of primitive topology types for processing by the rasterizer in a single draw operation.

12. The processing system of claim 11 , wherein the index buffer is further to include index data for one or more non-indexed primitive topology types, the indirection buffer to include topology type, vertex count, and offset into the vertex buffer for each of the one or more non-indexed primitive topology types.

13. The processing system of claim 11 , further comprising a geometry shader to support output of a plurality of primitive topology types in each of one or more output streams.

Assignees

• Intel Corp

Inventors

• Gierach John
• Venkatesh Abhishek
• Schluessler Travis
• Burke Devan
• Bar-On Tomer
• Apodaca Michael

Classifications

• G06T15/005

  General purpose rendering architectures · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T17/10

  Constructive solid geometry [CSG] using solid primitives, e.g. cylinders, cubes · CPC title