Systems and methods for enabling universal circuit board socket

Patent metadata

Field	Value
Publication number	US-10733134-B2
Application number	US-201816117559-A
Country	US
Kind code	B2
Filing date	Aug 30, 2018
Priority date	Aug 30, 2018
Publication date	Aug 4, 2020
Grant date	Aug 4, 2020

Abstract

In accordance with embodiments of the present disclosure, an information handling system may include a motherboard, a plurality of information handling resources communicatively coupled to the motherboard, a socket communicatively coupled to the motherboard and configured to receive one of a plurality of different types of interposers, wherein each of the plurality of interposers is configured to provide routing of electrical signals between the socket and a respective system on a chip communicatively coupled to such interposer, and a configuration module. The configuration module may be configured to receive identifying information associated with an interposer, of the plurality of interposers, communicatively coupled to the socket and based on the identifying information, configure the plurality of information handling resources for interoperability with a system on a chip communicatively coupled to the interposer.

First claim

What is claimed is:

1. An information handling system comprising:
a motherboard;
a plurality of information handling resources communicatively coupled to the motherboard;
a socket communicatively coupled to the motherboard and configured to receive one of a plurality of different types of interposers, wherein each of the plurality of interposers corresponds to a particular system on a chip (SOC) of a plurality of SOCs and is configured to provide routing of electrical signals between the socket and the particular SOC communicatively coupled to such interposer; and
a configuration module configured to:
receive identifying information associated with an interposer of the plurality of interposers, the interposer being communicatively coupled to the socket; and
based on the identifying information, configure the plurality of information handling resources for interoperability with the particular SOC communicatively coupled to the interposer, wherein the configuring the plurality of information handling resources includes configuring a power system of the information handling system including a programmable voltage regulator for interoperability with the particular SOC; and
wherein the configuring the plurality of information handling resources further includes determining that at least one information handling resource is not supported by the particular SOC, and disabling the at least one information handling resource.

2. The information handling system of claim 1 , wherein the configuration module is configured to receive the identifying information from the interposer via the socket.

3. The information handling system of claim 1 , wherein configuring the plurality of information handling resources comprises identifying firmware to be executed on the information handling system for interoperability with the particular SOC.

4. An interposer comprising:
a plurality of electrical conductive pathways for routing electrical connectors of a system on a chip (SOC) communicatively coupled to the interposer to respective counterpart electrical connectors of a circuit board socket to which the interposer is inserted; and
a non-transitory computer-readable medium configured to store identifying information associated with the interposer;
wherein the interposer is configured to communicate the identifying information to a configuration module communicatively coupled to the circuit board socket, such that the configuration module configures information handling resources communicatively coupled to the circuit board socket for interoperability with the SOC based on the identifying information, wherein the configuring the information handling resources includes configuring a power system including a programmable voltage regulator for interoperability with the SOC; and
wherein the configuring the information handling resources further includes determining that at least one information handling resource is not supported by the SOC, and disabling the at least one information handling resource.

5. A method comprising, in an information handling system having a motherboard, a plurality of information handling resources communicatively coupled to the motherboard, and a socket communicatively coupled to the motherboard and configured to receive one of a plurality of different types of interposers, wherein each of the plurality of interposers corresponds to a particular system on a chip (SOC) of a plurality of SOCs and is configured to provide routing of electrical signals between the socket and the particular SOC communicatively coupled to such interposer:
receiving identifying information associated with an interposer of the plurality of interposers, the interposer being communicatively coupled to the socket; and
based on the identifying information, configuring the plurality of information handling resources for interoperability with the particular SOC communicatively coupled to the interposer, wherein the configuring the plurality of information handling resources includes configuring a power system of the information handling system including a programmable voltage regulator for interoperability with the particular SOC; and
wherein the configuring the plurality of information handling resources further includes determining that at least one information handling resource is not supported by the particular SOC, and disabling the at least one information handling resource.

6. The method of claim 5 , further comprising receiving the identifying information from the interposer via the socket.

7. The method of claim 5 , wherein configuring the plurality of information handling resources comprises identifying firmware to be executed on the information handling system for interoperability with the particular SOC.

8. The method of claim 5 , wherein the particular SOC includes a chipset comprising a northbridge and a southbridge.

9. An article of manufacture comprising:
a non-transitory computer-readable medium; and
computer-executable instructions carried on the computer-readable medium, the instructions readable by a processor, the instructions, when read and executed, for causing the processor to, in an information handling system having a motherboard, a plurality of information handling resources communicatively coupled to the motherboard, and a socket communicatively coupled to the motherboard and configured to receive one of a plurality of different types of interposers, wherein each of the plurality of interposers corresponds to a particular system on a chip (SOC) of a plurality of SOCs is configured to provide routing of electrical signals between the socket and the particular SOC communicatively coupled to such interposer:
receive identifying information associated with an interposer of the plurality of interposers, the interposer being communicatively coupled to the socket; and
based on the identifying information, configure the plurality of information handling resources for interoperability with the particular SOC communicatively coupled to the interposer, wherein the configuring the plurality of information handling resources includes configuring a power system of the information handling system including a programmable voltage regulator for interoperability with the particular SOC; and
wherein the configuring the plurality of information handling resources further includes determining that at least one information handling resource is not supported by the particular SOC, and disabling the at least one information handling resource.

10. The article of claim 9 , wherein the instructions are further executable for receiving the identifying information from the interposer via the socket.

11. The article of claim 9 , wherein configuring the plurality of information handling resources comprises identifying firmware to be executed on the information handling system for interoperability with the particular SOC.

12. The article of claim 9 , wherein the particular SOC includes a chipset comprising a northbridge and a southbridge.

13. The information handling system of claim 1 , wherein the particular SOC includes a chipset comprising a northbridge and a southbridge.

14. The interposer of claim 4 , wherein the SOC includes a chipset comprising a northbridge and a southbridge.

Assignees

• Dell Products Lp

Inventors

• Nikazm Ayedin
• Radhakrishnan Ramesh

Classifications

• G06F15/7807

  System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package · CPC title

• G06F13/42 Primary

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title

• G06F13/409 Primary

  Mechanical coupling (back panels H05K7/1438) · CPC title