Measuring internal voltages of packaged electronic devices

Patent metadata

Field	Value
Publication number	US-10732660-B2
Application number	US-201916526801-A
Country	US
Kind code	B2
Filing date	Jul 30, 2019
Priority date	Oct 25, 2017
Publication date	Aug 4, 2020
Grant date	Aug 4, 2020

Abstract

An method comprising activating an internal switch within a packaged electronic device to connect to a reference ground of an internal voltage source to a first input of an analog front end, receiving an external ground potential voltage at a first package pin of the packaged electronic device, generating a zero detector output signal for the packaged electronic device at a second package pin, activating the internal switch to connect the first input of the analog front end to the internal voltage source, receiving a second voltage level at the first package pin that generates a second output signal that matches the zero detector output signal, and receiving trim instructions to trim an internal voltage generated by the internal voltage source to a voltage level that is closer to a target voltage level.

First claim

What is claimed is:

1. A packaged electronic device having:
an internal switch and a first package pin;
an analog front end coupled to the internal switch and the first package pin;
an internal voltage source that is not directly connected to any package pin of the packaged electronic device; and
a second package pin that produces an output signal based on an input voltage of the analog front end,
wherein the packaged electronic device is configured to:
receive an instruction to activate the internal switch to connect to a reference ground of the internal voltage source to a first input of the analog front end;
receive an external ground potential voltage at the first package pin of the packaged electronic device;
generate a zero detector output signal for the packaged electronic device at the second package pin;
receive a second instruction to activate the internal switch to connect the first input of the analog front end to the internal voltage source;
receive a second voltage level at the first package pin that generates a second output signal at the second package pin that matches the zero detector output signal, wherein the second voltage level differs from the external ground potential voltage; and
receive trim instructions to trim an internal voltage generated by the internal voltage source to a voltage level that is closer to a target voltage level.

2. The packaged electronic device of claim 1 , wherein the packaged electronic device further comprises a delta sigma modulator that is coupled to the analog front end, the internal voltage source, and the second package pin.

3. The packaged electronic device of claim 1 , wherein the packaged electronic device is further configured to:
receive a third voltage level at the target voltage level at the first package pin to generate a third output signal;
compare the third output signal to the zero detector output signal; and
receive trim instructions to trim the internal voltage when the third output signal differs from the zero detector output signal.

4. The packaged electronic device of claim 1 , wherein the zero detector output signal is a digital signal.

5. The packaged electronic device of claim 1 , wherein the zero detector output signal is an analog voltage.

6. The packaged electronic device of claim 1 , wherein the packaged electronic device is an isolation amplifier.

7. The packaged electronic device of claim 1 , wherein the internal voltage source is a bandgap reference voltage source.

8. The packaged electronic device of claim 1 , wherein the first package pin couples to a second input of the analog front end.

9. A non-transitory memory on which instructions are stored, comprising instructions that when executed cause a processor to:
generate an instruction to send to a packaged electronic device to activate an internal switch to connect a reference ground of an internal voltage source to a first input of an analog front end of the packaged electronic device;
supply an external ground potential voltage to a first package pin of the packaged electronic device;
measure a zero detector output signal for the packaged electronic device from a second package pin;
generate a second instruction to send to the packaged electronic device to activate the internal switch to connect the first input of the analog front end to the internal voltage source;
supply a second voltage level to the first package pin that generates a second output signal that matches the zero detector output signal, wherein the second voltage level is differs from the external ground potential voltage; and
determine, based on the second voltage level, a trim amount for an internal voltage generated by the internal voltage source to be closer to a target voltage level.

10. The non-transitory memory of claim 9 , wherein the instructions further comprise instructions that when executed cause the processor to:
supply a third voltage level at the target voltage level at the first package pin to generate a third output signal;
compare the third output signal to the zero detector output signal; and
determine, based on comparing the third output signal, the trim amount for the internal voltage when the third output signal does not match the zero detector output signal.

11. The non-transitory memory of claim 9 , wherein the zero detector output signal is an analog voltage.

12. The non-transitory memory of claim 9 , wherein the zero detector output signal is a digital signal.

13. The non-transitory memory of claim 9 , wherein the first package pin is an input voltage package pin.

14. The non-transitory memory of claim 9 , wherein the packaged electronic device is an isolation amplifier or a delta sigma modulator.

15. The non-transitory memory of claim 9 , wherein the first package pin couples to a second input of the analog front end.

16. The non-transitory memory of claim 9 , wherein the internal voltage source is a bandgap reference voltage source that supplies the internal voltage to a modulator of the packaged electronic device.

17. A method comprising:
receiving an instruction to activate an internal switch within a packaged electronic device to connect to a reference ground of an internal voltage source to a first input of an analog front end;
receiving an external ground potential voltage at a first package pin of the packaged electronic device;
generating a zero detector output signal for the packaged electronic device at a second package pin;
receiving a second instruction to activate the internal switch to connect the first input of the analog front end to the internal voltage source;
receiving a second voltage level at the first package pin that generates a second output signal that matches the zero detector output signal, wherein the second voltage level is greater or less than the external ground potential voltage;
receiving trim instructions to trim an internal voltage generated by the internal voltage source to a voltage level that is closer to a target voltage level; and
trimming the internal voltage based on the trim instructions.

18. The method of claim 17 , further comprising:
receiving a third voltage level at the target voltage level at the first package pin to generate a third output signal;
comparing the third output signal to the zero detector output signal; and
receiving trim instructions to trim the internal voltage when the third output signal does not match the zero detector output signal.

19. The method of claim 17 , wherein the zero detector output signal is either an analog voltage or a digital signal.

20. The method of claim 17 , wherein the internal voltage source is a bandgap reference voltage source that supplies the internal voltage to a modulator of the packaged electronic device.

Assignees

• Texas Instruments Inc

Inventors

• Jankowski Maciej Piotr
• Cao Peng

Classifications

• H03M3/494

  Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems · CPC title

• G01R31/2874

  related to temperature · CPC title

• H03M3/30

  Delta-sigma modulation · CPC title

• G05F3/16 Primary

  being semiconductor devices · CPC title

• G01R31/2856

  Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM] · CPC title