Modulation agnostic digital hybrid mode power amplifier system and method

Patent metadata

Field	Value
Publication number	US-10728066-B2
Application number	US-201715827794-A
Country	US
Kind code	B2
Filing date	Nov 30, 2017
Priority date	Dec 21, 2009
Publication date	Jul 28, 2020
Grant date	Jul 28, 2020

Abstract

A RF-digital hybrid mode power amplifier system for achieving high efficiency and high linearity in wideband communication systems is disclosed. The present invention is based on the method of adaptive digital predistortion to linearize a power amplifier in the RF domain. The present disclosure enables a power amplifier system to be field reconfigurable and support multi-modulation schemes (modulation agnostic), multi-carriers and multi-channels. As a result, the digital hybrid mode power amplifier system is particularly suitable for wireless transmission systems, such as base-stations, repeaters, and indoor signal coverage systems, where baseband I-Q signal information is not readily available.

First claim

We claim:

1. A digital predistortion system for linearizing the output of power amplifiers comprising:
input signal suitable for wireless communications;
at least one power amplifier for outputting an amplified signal;
at least one feedback signal derived from the amplified signal including a representation of a noise characteristic of the at least one power amplifier;
estimator logic responsive to the at least one feedback signal for generating predistortion coefficients a ij , based at least in part on feedback path delay determined from the correlation given by the equation

c
⁡

(
m
)

=

∑

i
=
0

N
-
1

⁢

sign
⁡

(



x
⁡

(

i
+
1

)



-



x
⁡

(
i
)



)

⁢

sign
⁡

(



y
⁡

(

i
+
m
+
1

)



-



y
⁡

(

i
+
m

)



)

where C(m) is a correlation function, x(n) represents transmission data, y(n) represents feedback data, c(m) is a correlation function, N is a number of data per block, m is a variable representing time, i is a counter for summation, and n(delay) is a delay determined by the value of m where C(m) is maximized; and
digital predistortion logic for predistorting the input signal and for supplying a predistorted signal to the at least one power amplifier, wherein the digital predistortion logic complies with the equation:

z
⁡

(
n
)

=

∑

i
=
0

n
-
1

⁢

x
t

⁡

(

n
-
i

)

⁢

(

∑

j
=
0

k
-
1

⁢

a
ij

⁢



x
t

⁡

(

n
-
i

)



j

)

where z(n) is a predistortion function, n is a variable representing time, x t is the input signal, i and j are counters for summation, and a ij are the predistortion coefficients determined by the estimator logic.

2. The digital predistortion system of claim 1 configured for base station applications further comprising a digital field programmable gate array that includes one or more of a digital up-converter, a crest factor reduction, a predistorter, or a digital quadrature modulator.

3. The digital predistortion system of claim 1 configured for repeater applications further comprising a digital field programmable gate array that includes at least one of a digital quadrature demodulator, a crest factor reduction, a predistorter, or a digital quadrature modulator.

4. The digital predistortion system of claim 1 further comprising a digital field programmable gate array that provides predistortion that compensates adaptively for both nonlinearity and memory effects by generating asy

Assignees

• Dali Systems Co Ltd

Inventors

• Kim Wan Jong
• Cho Kyoung Joon
• Stapleton Shawn Patrick
• Xiao Ying

Classifications

• H03F1/304 Primary

  and using digital means · CPC title

• H04L25/03343

  Arrangements at the transmitter end · CPC title

• H03F2201/3227

  Adaptive predistortion based on amplitude, envelope or power level feedback from the output of the main amplifier · CPC title

• H03F2201/3215

  To increase the output power or efficiency · CPC title

• H04W24/02

  Arrangements for optimising operational condition · CPC title