Power converter

Patent metadata

Field	Value
Publication number	US-10727729-B2
Application number	US-201515745265-A
Country	US
Kind code	B2
Filing date	Sep 3, 2015
Priority date	Sep 3, 2015
Publication date	Jul 28, 2020
Grant date	Jul 28, 2020

Abstract

A power converter includes: a power converter main circuit that includes semiconductor switching elements; gate drive circuits driving the semiconductor switching elements, respectively; and one or a plurality of impedance element groups connected between at least one pair of the gate drive circuits. At least one of the gate drive circuits includes a detector that detects a voltage across the impedance element group, and changes the driving speed of the semiconductor switching elements in accordance with an output of the detector.

First claim

The invention claimed is:

1. A power converter comprising:
a power converter main circuit including two or more semiconductor switching elements;
gate drive circuits, each of which drives a corresponding one of the semiconductor switching elements; and
one or a plurality of impedance elements electrically connected between at least one pair of the gate drive circuits, wherein
at least one of the gate drive circuits includes a detector to detect a voltage across the impedance elements or a current flowing through the impedance elements, and changes a driving speed of the semiconductor switching elements in accordance with an output of the detector.

2. The power converter according to claim 1 , wherein
the power converter main circuit includes a multi-level circuit corresponding to one phase or a plurality of phases to select a potential of any one of two or more DC terminals and output the selected potential to a load,
the multi-level circuit includes two or more semiconductor switching elements connected in series, and
the impedance elements are disposed between the gate drive circuits belonging to a same phase.

3. The power converter according to claim 2 , wherein
the multi-level circuit is a two-level circuit to select a potential of either one of an upper DC terminal and a lower DC terminal and output the selected potential to the load,
the two-level circuit includes a first semiconductor switching element and a second semiconductor switching element sequentially connected in series between the upper DC terminal and the lower DC terminal, and
a connection point of the first semiconductor switching element and the second semiconductor switching element is connected to the load.

4. The power converter according to claim 2 , wherein
the multi-level circuit is a three-level circuit to select a potential of any one of an upper DC terminal, an intermediate DC terminal, and a lower DC terminal and output the selected potential to the load,
the three-level circuit includes:
first, second, third, and fourth semiconductor switching elements sequentially connected in series between the upper DC terminal and the lower DC terminal;
a first diode element connected between the intermediate DC terminal and a connection point of the first semiconductor switching element and the second semiconductor switching element; and
a second diode element connected between the intermediate DC terminal and a connection point of the third semiconductor switching element and the fourth semiconductor switching element, and
a connection point of the second semiconductor switching element and the third semiconductor switching element is connected to the load.

5. The power converter according to claim 1 , wherein
the power converter main circuit includes a multi-level circuit corresponding to a plurality of phases to select a potential of any one of two or more DC terminals and output the selected potential to a load,
the multi-level circuit includes two or more semiconductor switching elements connected in series for each phase, and
the impedance elements are disposed between the gate drive circuits belonging to different phases.

6. The power converter according to claim 5 , wherein
the multi-level circuit is a two-level circuit to select a potential of either one of an upper DC terminal and a lower DC terminal and output the selected potential to the load,
the two-level circuit includes a first semiconductor switching element and a second semiconductor switching element sequentially connected in series between the upper DC terminal and the lower DC terminal, and
a connection point of the first semiconductor switching element and the second semiconductor switching element is connected to the load.

7. The power converter according to claim 5 , wherein
the multi-level circuit is a three-level circuit to select a potential of any one of an upper DC terminal, an intermediate DC terminal, and a lower DC terminal and output the selected potential to the load,
the three-level circuit includes:
first, second, third, and fourth semiconductor switching elements sequentially connected in series between the upper DC terminal and the lower DC terminal;
a first diode element connected between the intermediate DC terminal and a connection point of the first semiconductor switching element and the second semiconductor switching element; and
a second diode element connected between the intermediate DC terminal and a connection point of the third semiconductor switching element and the fourth semiconductor switching element, and
a connection point of the second semiconductor switching element and the third semiconductor switching element is connected to the load.

8. The power converter according to claim 1 , wherein the gate drive circuit increases the driving speed of the semiconductor switching element when a voltage transmitted from the impedance element to the gate drive circuit is lower than a reference voltage.

9. The power converter according to claim 1 , wherein the gate drive circuit reduces the driving speed of the semiconductor switching element when a voltage transmitted from the impedance element to the gate drive circuit is higher than a reference voltage.

10. The power converter according to claim 1 , wherein
at least one of the gate drive circuits includes a storage to store information on whether a voltage transmitted from the impedance elements is higher or lower than a reference voltage, and
the gate drive circuit that includes the storage changes the driving speed of the semiconductor switching element on a basis of the information stored in the storage.

Assignees

• Mitsubishi Electric Corp

Inventors

• Nakashima Yukio
• Miki Takayoshi

Classifications

• H02M1/44 Primary

  Circuits or arrangements for compensating for electromagnetic interference in converters or inverters · CPC title

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title

• H02M1/0054

  Transistor switching losses (periodically suspending operation of switching converter in low power mode H02M1/0035) · CPC title

• H03K17/08122

  in field-effect transistor switches · CPC title

• H02M7/487

  Neutral point clamped inverters · CPC title