Rewiring method for semiconductor

Patent metadata

Field	Value
Publication number	US-10727112-B2
Application number	US-201716338665-A
Country	US
Kind code	B2
Filing date	Sep 28, 2017
Priority date	Sep 30, 2016
Publication date	Jul 28, 2020
Grant date	Jul 28, 2020

Abstract

A method for rewiring of semiconductor devices is provided, in which deviations of electrical connection terminals ( 211, 212, 221, 222, 231, 232 ) on a carrier ( 100 ) are calculated and corrected by forming rewiring structures on the electrical connection terminals by mask-free photolithography. A wiring layer and/or solder balls ( 700 ) is/are then formed on the rewiring structures by processing the carrier ( 100 ) in a monolithic manner using mask-based photolithography. In this way, the combined use of mask-free photolithography and mask-based photolithography allows for higher efficiency and a shorter process cycle, compared to only using mask-free photolithography.

First claim

What is claimed is:

1. A method for rewiring of semiconductor devices, comprising the steps of:
1) arranging a carrier for bearing a plurality of semiconductor devices, each of the semiconductor devices having a plurality of electrical connection terminals;
2) measuring positions of the plurality of electrical connection terminals relative to the carrier, and obtaining deviations of the plurality of electrical connection terminals by comparing the measured positions with standard positions of the plurality of electrical connection terminals relative to the carrier;
3) forming corrected rewiring structures on the plurality of electrical connection terminals by performing a mask-free photolithography process based on the obtained deviations and deviation-free standard wiring patterns of the semiconductor devices; and
4) forming a wiring layer and/or solder balls on the corrected rewiring structures by performing a mask-based photolithography process in a unified manner based on deviation-free standard positions of the semiconductor devices on the carrier.

2. The method for rewiring of semiconductor devices of claim 1 , wherein step 3) comprises:
depositing a first dielectric layer;
coating a first photoresist layer on the first dielectric layer;
forming a plurality of first-photoresist patterns in the first photoresist layer by performing the mask-free photolithography process based on the deviations obtained from step 2), wherein each of the plurality of first-photoresist patterns is aligned with a corresponding one of the plurality of electrical connection terminals;
etching the first dielectric layer with the first photoresist layer serving as a mask and thereby forming a plurality of first openings in the first dielectric layer, each of the plurality of first openings exposing a corresponding one of the plurality of electrical connection terminals; removing the first photoresist layer;
coating a second photoresist layer;
forming a plurality of second-photoresist patterns in the second photoresist layer by performing the mask-free photolithography process based on the deviations and the deviation-free standard wiring patterns of the semiconductor devices, thereby defining corrected areas for the rewiring structures; and
filling a metal in the corrected areas to form the rewiring structures.

3. The method for rewiring of semiconductor devices of claim 2 , wherein step 4) comprises:
depositing a second dielectric layer;
coating a third photoresist layer on the second dielectric layer;
forming a plurality of third-photoresist patterns in the third photoresist layer by performing the mask-based photolithography process, each of the plurality of third-photoresist patterns corresponding to one ball pad;
etching the second dielectric layer with the third photoresist layer serving as a mask and thereby forming a plurality of second openings in the second dielectric layer, each of the plurality of second openings exposing a portion of a corresponding one of the rewiring structures; and
forming the solder balls on the exposed portions of the rewiring structures.

4. The method for rewiring of semiconductor devices of claim 3 , wherein the areas for the rewiring structures are defined such that only the rewiring structures are exposed in the plurality of second openings in step 4).

5. The method for rewiring of semiconductor devices of claim 1 , wherein the semiconductor devices are dies.

6. A method for rewiring of semiconductor devices, comprising the steps of:
arranging a carrier for bearing a plurality of semiconductor devices, each of the semiconductor devices having a plurality of electrical connection terminals;
measuring positions of the plurality of electrical connection terminals relative to the carrier;
obtaining deviations of the plurality of electrical connection terminals by comparing the measured positions with standard positions of the plurality of electrical connection terminals relative to the carrier; and
comparing the deviations with a predetermined critical deviation range and forming corrected rewiring structures on the plurality of electrical connection terminals by photolithography based on the comparison and based on deviation-free standard wiring patterns of the semiconductor devices, wherein forming the rewiring structures comprises:
processing one(s) of the plurality of electrical connection terminals whose deviation(s) is/are below the critical deviation range by performing a mask-based photolithography process;
processing one(s) of the plurality of electrical connection terminals whose deviation(s) is/are beyond the critical deviation range by performing a mask-free photolithography process; and
processing each of one(s) of the plurality of electrical connection terminals whose deviation(s) is/are within the critical deviation range by performing one of the mask-based and mask-free photolithography processes whichever is more frequently employed to process surrounding electrical connection terminals; and
forming a wiring layer and/or solder balls on the corrected rewiring structures by performing the mask-based photolithography process in a unified manner based on deviation-free standard wiring patterns of the semiconductor devices on the carrier.

7. The method for rewiring of semiconductor devices of claim 6 , wherein in a X-Y-Z three-dimensional system with two linear directions perpendicular to each other and both parallel to a surface of the carrier respectively as X and Y axes and with a linear direction perpendicular to the surface of the carrier as a Z axis, the deviations comprise at least one of X-deviations, Y-deviations and RZ-deviations, where RZ denotes a rotational direction about the Z-axis.

8. The method for rewiring of semiconductor devices of claim 6 , wherein forming the rewiring structures comprises:
processing one(s) of the plurality of electrical connection terminals whose deviation(s) is/are beyond the critical deviation range by performing the mask-free photolithography process; and
processing one(s) of the plurality of electrical connection terminals whose deviation(s) is/are below the critical deviation range by performing the mask-based photolithography process, concurrently with the plurality of electrical connection terminals that have been processed by performing the mask-free photolithography process being shielded;
wherein for each of one(s) of the plurality of electrical connection terminals whose deviation(s) is/are within the critical deviation range, counting a number of neighboring electrical connection terminals to be treated by the mask-based photolithography process and a number of neighboring electrical connection terminals to be treated by the mask-free photolithography process, and performing the mask-based photolithography process if the number of neighboring electrical connection terminals to be treated by the mask-based photolithography process is greater than the number of neighboring electrical connection terminals to be treated by the mask-free photolithography process, or performing the mask-free photolithography process if the number of neighboring electrical connection terminals to be treated by the mask-based photolithography process is smaller than the number of neighboring electrical connection terminals to be treated by the mask-free photolithography process.

9. The method for rewiring of semiconductor devices of claim 6 , wherein forming the rewiring structures comprises:
processing one(s) of the plurality of electrical connection terminals whose deviation(s) is/are below the critical deviation range by performing the mask-based photolithography process; processing one(s) of the plurality of electrical connection terminals whose deviatio

Assignees

• Shanghai Micro Electronics Equipment Group Co Ltd

Inventors

• Chen Yonghui
• Tang Shiyi

Classifications

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W70/09 Primary

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title