Self-aligned double patterning-aware routing in chip manufacturing

Patent metadata

Field	Value
Publication number	US-10726187-B2
Application number	US-201816143697-A
Country	US
Kind code	B2
Filing date	Sep 27, 2018
Priority date	Sep 27, 2018
Publication date	Jul 28, 2020
Grant date	Jul 28, 2020

Abstract

A method of generating a routing result to manufacture an integrated circuit using self-aligned double patterning includes generating an initial routing result that indicates a location and length of connections between components, and generating an initial constraint graph with trim shapes indicating gaps in the connections being represented as nodes and with arcs indicating relative position constraints between a pair of the nodes. The method also includes subdividing the initial constraint graph into two or more subgraphs, determining a final position of each of the nodes in the two or more subgraphs, and generating a routed design with the trim shapes having the final position of corresponding ones of the nodes relative to the connections and with extents filling in spaces between one or more of the trim shapes and associated connections. The routed design is provided for manufacture of the integrated circuit.

First claim

What is claimed is:

1. A computer-implemented method of generating a routing result to manufacture an integrated circuit using self-aligned double patterning, the method comprising:
generating, using a processor, an initial routing result that indicates a location and length of connections between components;
generating, using the processor, an initial constraint graph with trim shapes indicating gaps in the connections being represented as nodes and with arcs indicating relative position constraints between a pair of the nodes;
subdividing, using the processor, the initial constraint graph into two or more subgraphs;
determining, using the processor, a final position of each of the nodes in the two or more subgraphs;
generating, using the processor, a routed design with the trim shapes having the final position of corresponding ones of the nodes relative to the connections and with extents filling in spaces between one or more of the trim shapes and associated connections; and
providing the routed design for manufacture of the integrated circuit, wherein the subdividing the initial constraint graph is based on constraining movement of two or more of the nodes and pruning one or more arcs between the two or more of the nodes.

2. The computer-implemented method according to claim 1 , wherein the determining the final position of each of the nodes is based on an iterative process of positioning one of the nodes per iteration.

3. The computer-implemented method according to claim 2 , wherein the positioning one of the nodes is based on a type of the arc between the one of the nodes and a previously positioned one of the nodes.

4. The computer-implemented method according to claim 3 , wherein the positioning the one of the nodes includes maintaining a relative lateral position of the one of the nodes with respect to the previously positioned one of the nodes, changing the relative lateral position of the one of the nodes with respect to the previously positioned one of the nodes, or merging the one of the nodes with the previously positioned one of the nodes based on the type of the arc.

5. The computer-implemented method according to claim 1 , further comprising improving the routed design prior to providing the routed design for manufacture.

6. The computer-implemented method according to claim 5 , wherein the improving the routed design includes removing and re-routing connections or extents.

7. A system to generate a routing result to manufacture an integrated circuit using self-aligned double patterning, the system comprising:
a memory device configured to store an integrated circuit design; and
a processor configured to generate an initial routing result that indicates a location and length of connections between components of the integrated circuit design, to generate an initial constraint graph with trim shapes indicating gaps in the connections being represented as nodes and with arcs indicating relative position constraints between a pair of the nodes, to subdivide the initial constraint graph into two or more subgraphs, to determine a final position of each of the nodes in the two or more subgraphs, to generate a routed design with the trim shapes having the final position of corresponding ones of the nodes relative to the connections and with extents filling in spaces between one or more of the trim shapes and associated connections, and to provide the routed design for manufacture of the integrated circuit, wherein the processor is configured to subdivide the initial constraint graph based on constraining movement of two or more of the nodes and pruning one or more arcs between the two or more of the nodes.

8. The system according to claim 7 , wherein the processor is configured to determine the final position of each of the nodes based on an iterative process of positioning one of the nodes per iteration.

9. The system according to claim 8 , wherein the processor is configured to position one of the nodes during an iteration based on a type of the arc between the one of the nodes and a previously positioned one of the nodes.

10. The system according to claim 9 , wherein the processor is configured to position the one of the nodes during the iteration by maintaining a relative lateral position of the one of the nodes with respect to the previously positioned one of the nodes, changing the relative lateral position of the one of the nodes with respect to the previously positioned one of the nodes, or merging the one of the nodes with the previously positioned one of the nodes based on the type of the arc.

11. The system according to claim 7 , wherein the processor is further configured to improve the routed design prior to providing the routed design for manufacture.

12. The system according to claim 7 , wherein the processor is configured to improve the routed design based on removing and re-routing connections or extents.

13. A computer program product for generating a routing result to manufacture an integrated circuit using self-aligned double patterning, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to perform a method comprising:
generating an initial routing result that indicates a location and length of connections between components;
generating an initial constraint graph with trim shapes indicating gaps in the connections being represented as nodes and with arcs indicating relative position constraints between a pair of the nodes;
subdividing the initial constraint graph into two or more subgraphs;
determining a final position of each of the nodes in the two or more subgraphs; and
generating a routed design with the trim shapes having the final position of corresponding ones of the nodes relative to the connections and with extents filling in spaces between one or more of the trim shapes and associated connections, wherein the routed design is provided for manufacture of the integrated circuit, wherein the subdividing the initial constraint graph is based on constraining movement of two or more of the nodes and pruning one or more arcs between the two or more of the nodes.

14. The computer program product according to claim 13 , wherein the determining the final position of each of the nodes is based on an iterative process of positioning one of the nodes per iteration.

15. The computer program product according to claim 14 , wherein the positioning one of the nodes is based on a type of the arc between the one of the nodes and a previously positioned one of the nodes.

16. The computer program product according to claim 15 , wherein the positioning the one of the nodes includes maintaining a relative lateral position of the one of the nodes with respect to the previously positioned one of the nodes, changing the relative lateral position of the one of the nodes with respect to the previously positioned one of the nodes, or merging the one of the nodes with the previously positioned one of the nodes based on the type of the arc.

17. The computer program product according to claim 13 , further comprising improving the routed design prior to providing the routed design for manufacture, wherein the improving the routed design includes removing and re-routing connections or extents.

Assignees

• IBM

Inventors

• Pandey Diwesh
• Tellez Gustavo E
• Gao Shaodi

Classifications

• H10D89/10

  Integrated device layouts · CPC title

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title