Input device receiver with delta-sigma modulator

Patent metadata

Field	Value
Publication number	US-10725583-B2
Application number	US-201816107570-A
Country	US
Kind code	B2
Filing date	Aug 21, 2018
Priority date	Jun 30, 2016
Publication date	Jul 28, 2020
Grant date	Jul 28, 2020

Abstract

A processing system, and associated input device and method are disclosed suitable for reducing a receiver size within the input device. The processing system comprises a delta-sigma modulator comprising one or more input nodes configured to receive a signal based on a sensor signal received from at least a first sensor electrode of the plurality of sensor electrodes. The delta-sigma modulator further comprises an integrator coupled with the one or more input nodes and configured to produce an integration signal, a quantizer coupled with an output of the integrator and configured to quantize the integration signal, and a feedback digital-to-analog converter (DAC) controlled based by the quantizer. The processing system further comprises a digital filter coupled with an output of the delta-sigma modulator and configured to mitigate a quantization noise of the quantizer.

First claim

What is claimed is:

1. A processing system for an input device, the processing system comprising:
a mixer configured to:
downconvert a first signal derived from a sensor signal received by the input device, wherein the first signal is a mirrored current signal generated by a current conveyor from the sensor signal; and
output a processed signal;

a delta-sigma modulator configured to receive the processed signal, the delta-sigma modulator comprising a quantizer; and
a digital filter coupled with an output of the delta-sigma modulator and configured to mitigate a quantization noise of the quantizer.

2. The processing system of claim 1 , wherein the delta-sigma modulator is included in receiver circuitry of the processing system.

3. The processing system of claim 1 , wherein the delta-sigma modulator further comprises a differential modulator configured to receive the processed signal.

4. The processing system of claim 1 , wherein the delta-sigma modulator further comprises a first input node and a second input node, the processed signal is received with one of the first input node and the second input node of the delta-sigma modulator, and a first common mode capacitor and a second common mode capacitor are coupled between the first input node and the second input node.

5. The processing system of claim 1 , wherein the processed signal has substantially no frequency component.

6. The processing system of claim 1 , wherein the mixer comprises a plurality of switches configured to downconvert the first signal by performing a polarity-switching function.

7. An input device comprising:
a sensor electrode;
a processing system coupled to the sensor electrode, the processing system comprising:
a mixer configured to:
downconvert a first signal derived from a sensor signal received by the sensor electrode, wherein the first signal is a mirrored current signal generated by a current conveyor from the sensor signal; and
output a processed signal;

 a delta-sigma modulator configured to receive the processed signal, the delta-sigma modulator comprising a quantizer; and
a digital filter coupled with an output of the delta-sigma modulator and configured to mitigate a quantization noise of the quantizer.

8. The input device of claim 7 , wherein the delta-sigma modulator is included in receiver circuitry of the processing system.

9. The input device of claim 7 , wherein the delta-sigma modulator further comprises a differential modulator configured to receive the processed signal.

10. The input device of claim 9 , wherein the processing system is further configured to provide the processed signal comprising continuous time output signals to the differential modulator of the delta-sigma modulator.

11. The input device of claim 7 , wherein the processed signal has substantially no frequency component.

12. The input device of claim 7 , wherein the delta-sigma modulator further comprises a first input node and a second input node, the processed signal is received with one of the first input node and the second input node of the delta-sigma modulator, and a first common mode capacitor and a second common mode capacitor are coupled between the first input node and the second input node.

13. The input device of claim 7 , wherein the mixer comprises a plurality of switches configured to downconvert the first signal by performing a polarity-switching function.

14. A method comprising:
generating, using a mixer, a processed signal by downconverting a first signal derived from a sensor signal received by an input device, wherein the first signal is a mirrored current signal generated by a current conveyor from the sensor signal;
quantizing, using a delta-sigma modulator, an integration signal, wherein the integration signal is based on the processed signal; and
mitigating, using a digital filter, quantization noise of the delta-sigma modulator.

15. The method of claim 14 , further comprising:
controlling a feedback digital-to-analog converter (DAC) based on the quantization of the integration signal, the feedback DAC coupled with one or more input nodes of the delta-sigma modulator.

16. The method of claim 14 , wherein the processed signal has substantially no frequency component.

17. The method of claim 14 , wherein generating the processed signal by downconverting the first signal comprises controlling a plurality of switches to perform a polarity-switching function.

18. The method of claim 14 , further comprising receiving the processed signal with one of a first input node and a second input node of the delta-sigma modulator, and wherein a first common mode capacitor and a second common mode capacitor are coupled between the first input node and the second input node.

Assignees

• Synaptics Inc

Inventors

• Bohannon Eric Scott
• Bell Jr Marshall J
• Yang Yihong

Classifications

• G06F3/041 Primary

  Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means · CPC title

• G06F3/04184

  Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally · CPC title

• G06F3/0446

  using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes · CPC title

• G06F3/04182 Primary

  Filtering of noise external to the device and not generated by digitiser components · CPC title

• G06F3/0445

  using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer · CPC title