Communication apparatus, communication method, program, and communication system

Patent metadata

Field	Value
Publication number	US-10721022-B2
Application number	US-201716099306-A
Country	US
Kind code	B2
Filing date	May 2, 2017
Priority date	May 18, 2016
Publication date	Jul 21, 2020
Grant date	Jul 21, 2020

Abstract

A master includes a transmission/reception unit which transmits/receives a signal to/from a slave, and an error detection unit which detects error occurrence by performing parity check to data received by the transmission/reception unit. Then, the error detection unit performs error detection assuming one bit of 2-bit parity included in the data received by the transmission/reception unit as even parity, and the other bit as odd parity. The present technology can be applied to a bus IF which performs communication in compliance with, for example, an I3C standard.

First claim

The invention claimed is:

1. A communication device comprising:
transmission and reception circuitry configured to communicate with an external communication device via a data signal line and a clock signal line, the communication including transmitting and receiving data via the data signal line, the data including an expected parity and a payload, the expected parity including a first expected parity bit and a second expected parity bit; and
control circuitry configured to perform a parity check to received data by calculating a first calculated parity bit and calculating a second calculated parity bit, and by comparing the first expected parity bit to the first calculated parity bit and comparing the second expected parity bit to the second calculated parity bit,
wherein one of the first calculated parity bit or the second calculated parity bit is calculated by applying an XOR function to one of all odd payload bits or all even payload bits, and the other one of the first calculated parity bit or the second calculated parity bit is calculated by applying an XOR function to the other of all odd payload bits or all even payload bits adding 1.

2. The communication device according to claim 1 , wherein the control circuitry is configured to calculate the first calculated parity bit using the XOR function of all odd payload bits, and to calculate the second calculated parity bit using the XOR function of all even payload bits adding 1.

3. The communication device according to claim 1 , wherein the control circuitry is configured to calculate the first calculated parity bit using the XOR function of all odd payload bits adding 1 , and to calculate the second calculated parity bit using the XOR function of all even payload bits.

4. The communication device according to claim 1 , wherein the control circuitry is configured to determine that an error has occurred when the first expected parity bit does not match the first calculated parity bit, and/or the second expected parity bit does not match the second calculated parity bit.

5. The communication device according to claim 4 , wherein, in a case where the control circuitry determines that the error has occurred, the control circuitry causes the transmission and reception circuitry to restart communication with the external communication device.

6. The communication device according to claim 4 , wherein, in the case where the control circuitry determines that the error has occurred, the control circuitry causes the transmission and reception circuitry not to transmit an acknowledgement signal to the external communication device.

7. The communication device according to claim 1 , wherein, in a case where the control circuitry determines that an error has occurred, the transmission and reception circuitry ignores a predetermined number of bits after not transmitting an acknowledgement signal.

8. The communication device according to claim 1 , wherein the transmission and reception circuitry is configured to communicate in an SDR mode and an HDR mode, data communication being performed at a first transfer rate in the SDR mode, the data communication being performed at a second transfer rate higher than the first transfer rate in the HDR mode.

9. The communication device according to claim 8 , wherein the control circuitry is configured to perform the parity check to the received data in the HDR mode.

10. A communication device comprising:
transmission and reception circuitry configured to communicate with an external communication device via a data signal line and a clock signal line, the communication including transmitting and receiving data via the data signal line, the data including a parity and a payload, the parity including a first parity bit and a second parity bit; and
control circuitry configured to calculate the parity for the data to be transmitted by the transmission and reception circuitry by calculating the first parity bit and calculating the second parity bit, and configured to append the parity to the payload,
wherein one of the first parity bit or the second parity bit is calculated by applying an XOR function to one of all odd payload bits or all even payload bits, and the other one of the first parity bit or the second parity bit are calculated by applying an XOR function to the other of all odd payload bits or all even payload bits adding 1.

11. The communication device according to claim 10 , wherein the control circuitry is configured to calculate the first parity bit using the XOR function of all odd payload bits, and to calculate the second parity bit using the XOR function of all even payload bits adding 1.

12. The communication device according to claim 10 , wherein the control circuitry is configured to calculate the first parity bit using the XOR function of all odd payload bits adding 1, and to calculate the second parity bit using the XOR function of all even payload bits.

13. The communication device according to claim 10 , wherein the control circuitry is configured to determine whether an error has occurred and, in a case where the control circuitry determines that the error has occurred, the control circuitry causes the transmission and reception circuitry to restart communication with the external communication device.

14. The communication device according to claim 10 , wherein the control circuitry is configured to determine that an error has occurred by detecting the absence of an acknowledgement signal from the external communication device.

15. The communication device according to claim 10 , wherein the transmission and reception circuitry is configured to communicate in an SDR mode and an HDR mode, data communication being performed at a first transfer rate in the SDR mode, the data communication being performed at a second transfer rate higher than the first transfer rate in the HDR mode.

16. The communication device according to claim 15 , wherein the control circuitry is configured to calculate the parity in the HDR mode.

17. A communication system, comprising:
a first communication device, including:
first transmission and reception circuitry configured to communicate via a data signal line and a clock signal line, the communication including transmitting and receiving data via the data signal line, the data including an expected parity and a payload, the expected parity including a first expected parity bit and a second expected parity bit, and
first control circuitry configured to calculate the expected parity for the data to be transmitted by the first transmission and reception circuitry, and to add the expected parity to the payload; and

a second communication device, including
second transmission and reception circuitry configured to communicate with the first communication device via the data signal line and the clock signal line, the communication including transmitting and receiving the data via the data signal line, and
second control circuitry configured to perform a parity check to the data received by the second transmission and reception circuitry by calculating a first calculated parity bit and calculating a second calculated parity bit, and by comparing the first expected parity bit to the first calculated parity bit and comparing the second expected parity bit to the second calculated parity bit,

wherein one of the first expected parity bit or the second expected parity bit is calculated by applying an XOR function to one of all odd payload bits or all even payload bits, and the other one of the first expected parity bit or the second expected parity bit is calculated

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Takahashi Hiroo
• Yokokawa Takashi
• Lee Sonfun
• Koshisaka Naohiro

Classifications

• G06F11/1032 Primary

  Simple parity · CPC title

• H04L1/08

  by repeating transmission, e.g. Verdan system {(H04L1/1858 and H04L1/189 take precedence)} · CPC title

• H04L1/0061 Primary

  Error detection codes · CPC title